11 commits

Author	SHA1	Message	Date
DrasLorus	03e6fbd1f7	Merge branch 'main' into devel	2022-09-21 15:53:01 +02:00
DrasLorus	992b7cdbfe	Increase output size, enlarge kn_values table to support more stages	2022-07-06 12:30:25 +02:00
DrasLorus	b72065e052	Add experimental support for MSVC ... - Add an option `ENABLE_DEPFETCH` to use the CMake module FetchContent to pull dependencies from external locations.	2022-06-05 17:05:36 +02:00
DrasLorus	d9f80fc165	Enable support of GNU v4.6 and (consequently) of Vivado HLS 2019.1 ... - Also disable TCL unit COSIM test. Can be enable by turning 'true' to false in the CMakeLists, - v4.6 doesn't support C++14, nor some C++11, so some hacky ways have been found. Unit test has been updated but still works and coverage is good (94%, the 6% beeing exeption handling, unrelevant in HLS).	2022-05-16 19:02:23 +02:00
Camille Monière	cb06836072	Formatting	2022-04-21 15:32:39 +02:00
DrasLorus	b10024004e	Fix include bugs and revert to lower quantization ... - Only 2 bits more than input is enough, CoSimulation works (test succeed, even if VitisHLS reports failure on some computers...). - Rename `catch_common` to `catch_common_${PROJECT_NAME}` to avoid problems when included in a cmake top project. - Add a sanity check to unit tests to avoid SEGV.	2022-04-20 20:05:09 +02:00
Camille Monière	eaa9177962	Modify code to comply to buggy Vivado_HLS 2019.1 ... - For whatever reasons, v2019.1 can C-Simulate CCordicAbs, but cannot C-Synthetize it. So the process member function have been mirrored to a static process function in the top level, called directly. It just works. - The TCL script have been amended to support both Vivado_HLS 2019.1 and Vitis_HLS 2020.2 (maybe .1 also, but hasn't been tested). - The CMake project works and is validated for G++ > 6.2, so can't be used with vivado less than 2020.1 (which use 4.6.3). This vivado version must be used with the TCL script directly. - A custom target `run_hls` has been created to call vitis_hls 2020.2 if ENABLE_XILINX and ENABLE_TESTING have been specified. It is called by ctest by default. It can produce an IP (option IP_XILINX) and run Vivado implementation design flow (option IMPL_XILINX).	2022-04-19 19:07:06 +02:00
Camille Monière	4460de8fb5	Widen output of 1 bit to pass Co-Simulaton	2022-04-17 17:14:15 +02:00
DrasLorus	c68e3e9372	Finalize a top level IP ... - Must be tested on hardware, cosimulation testbench is buggy.	2022-04-15 18:59:42 +02:00
Camille Monière	ee535621f9	Working unit tests	2022-04-14 17:21:16 +02:00
Camille Monière	5b0f6d9a6b	First Working and tested release	2022-04-13 19:38:34 +02:00