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Widen output of 1 bit to pass Co-Simulaton
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2 changed files with 3 additions and 3 deletions
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@ -18,5 +18,5 @@ set_clock_uncertainty 2
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#source "./cordicabs_16_4_6/solution/directives.tcl"
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csim_design -argv "${ROOT_DIR}/data/input.dat" -clean -O
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csynth_design
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# cosim_design -O -argv "${ROOT_DIR}/data/input.dat"
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cosim_design -O -argv "${ROOT_DIR}/data/input.dat"
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export_design -format ip_catalog
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@ -46,8 +46,8 @@ public:
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static constexpr const unsigned In_W = TIn_W;
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static constexpr const unsigned In_I = TIn_I;
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static constexpr const unsigned Out_W = In_W + 2;
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static constexpr const unsigned Out_I = In_I + 2;
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static constexpr const unsigned Out_W = In_W + 3;
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static constexpr const unsigned Out_I = In_I + 3;
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static constexpr const unsigned nb_stages = Tnb_stages;
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static constexpr unsigned kn_i = unsigned(kn_values[nb_stages - 1] * double(1U << 3)); // 3 bits are enough
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