Widen output of 1 bit to pass Co-Simulaton

This commit is contained in:
Camille Monière 2022-04-17 17:14:15 +02:00
parent c68e3e9372
commit 4460de8fb5
Signed by: moniere
GPG key ID: 188DD5B072181C0F
2 changed files with 3 additions and 3 deletions

View file

@ -18,5 +18,5 @@ set_clock_uncertainty 2
#source "./cordicabs_16_4_6/solution/directives.tcl"
csim_design -argv "${ROOT_DIR}/data/input.dat" -clean -O
csynth_design
# cosim_design -O -argv "${ROOT_DIR}/data/input.dat"
cosim_design -O -argv "${ROOT_DIR}/data/input.dat"
export_design -format ip_catalog

View file

@ -46,8 +46,8 @@ public:
static constexpr const unsigned In_W = TIn_W;
static constexpr const unsigned In_I = TIn_I;
static constexpr const unsigned Out_W = In_W + 2;
static constexpr const unsigned Out_I = In_I + 2;
static constexpr const unsigned Out_W = In_W + 3;
static constexpr const unsigned Out_I = In_I + 3;
static constexpr const unsigned nb_stages = Tnb_stages;
static constexpr unsigned kn_i = unsigned(kn_values[nb_stages - 1] * double(1U << 3)); // 3 bits are enough