mirror of
https://github.com/DrasLorus/CORDIC_Abs_APFX.git
synced 2024-11-12 16:13:16 +01:00
Modify code to comply to buggy Vivado_HLS 2019.1
- For whatever reasons, v2019.1 can C-Simulate CCordicAbs, but cannot C-Synthetize it. So the process member function have been mirrored to a static process function in the top level, called directly. It just works. - The TCL script have been amended to support both Vivado_HLS 2019.1 and Vitis_HLS 2020.2 (maybe .1 also, but hasn't been tested). - The CMake project works and is validated for G++ > 6.2, so can't be used with vivado less than 2020.1 (which use 4.6.3). This vivado version must be used with the TCL script directly. - A custom target `run_hls` has been created to call vitis_hls 2020.2 if ENABLE_XILINX and ENABLE_TESTING have been specified. It is called by ctest by default. It can produce an IP (option IP_XILINX) and run Vivado implementation design flow (option IMPL_XILINX).
This commit is contained in:
Camille Monière
parent
4460de8fb5
commit
eaa9177962
GPG key ID:
188DD5B072181C0F
6 changed files with 259 additions and 31 deletions
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@ -18,27 +18,44 @@
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cmake_minimum_required (VERSION 3.16.0 FATAL_ERROR)
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# setting this is required
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set (CMAKE_CXX_STANDARD 14)
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set (CMAKE_CXX_STANDARD_REQUIRED ON)
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set (CMAKE_CXX_EXTENSIONS OFF)
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set (CMAKE_ARCHIVE_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}/../lib)
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set (CMAKE_LIBRARY_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}/../lib)
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set (CMAKE_RUNTIME_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}/../bin)
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set (CMAKE_EXPORT_COMPILE_COMMANDS true)
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project (
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CordicAbs
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LANGUAGES CXX
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VERSION 0.1
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)
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if ((CMAKE_CXX_COMPILER_ID STREQUAL "GNU") AND (CMAKE_CXX_COMPILER_VERSION VERSION_LESS 6.2))
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message (
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FATAL_ERROR
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"This project require a GNU compiler version greater than 6.2."
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"\nNote: If you tried to use g++-4.6.3 as provided by Xilinx Vivado v2019.1, use directly the TCL script "
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"in the folder `hls_files/cordicabs_16_4_6`."
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)
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endif ()
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set (CMAKE_CXX_STANDARD 14)
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set (CMAKE_CXX_STANDARD_REQUIRED ON)
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set (CMAKE_CXX_EXTENSIONS OFF)
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set (CMAKE_ARCHIVE_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}/../lib)
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set (CMAKE_LIBRARY_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}/../lib)
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set (CMAKE_RUNTIME_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}/../bin)
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# ##################################################################################################
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# Options
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# ##################################################################################################
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option (EXPORT_COMMANDS "export compile commands, for use with clangd for example." ON)
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option (ENABLE_XILINX "use Xilinx provided proprietary headers." OFF)
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if (ENABLE_XILINX)
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option (XILINX_COSIM "use TCL Vivado/Vitis HLS script to co-simulate the design." OFF)
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if (XILINX_COSIM)
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option (XILINX_IP "use TCL Vivado/Vitis HLS script to generate an IP." OFF)
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if (XILINX_IP)
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option (XILINX_IMPL "use TCL Vivado/Vitis HLS script to run design implementation." OFF)
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endif ()
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endif ()
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endif ()
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option (ENABLE_TESTING "use Catch2 in conjunction with CTest as a test suite." ON)
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option (ENABLE_SOFTWARE
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@ -70,11 +87,16 @@ if (ENABLE_XILINX)
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)
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if (XILINX_VER VERSION_GREATER_EQUAL "2020.1")
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set (AP_INCLUDE_DIR ${XILINX_HOME}/Vitis_HLS/${XILINX_VER}/include)
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set (AP_INCLUDE_DIR ${XILINX_HOME}/Vitis_HLS/${XILINX_VER}/include CACHE INTERNAL "Path to Xilinx includes" FORCE)
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find_program (XILINX_HLS vitis_hls HINTS ${XILINX_HOME}/Vitis_HLS/${XILINX_VER}/bin NO_CACHE REQUIRED)
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else ()
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set (AP_INCLUDE_DIR ${XILINX_HOME}/Vivado/${XILINX_VER}/include)
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message (
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FATAL_ERROR
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"Xilinx versions less than 2020.1 are not supported due to the outdated compiler version in use"
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)
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endif ()
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message (STATUS "AP headers must lie under ${AP_INCLUDE_DIR}")
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else ()
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set (
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AP_TYPES_HINT
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@ -127,4 +149,55 @@ if (ENABLE_TESTING)
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include (CTest)
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include (Catch)
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catch_discover_tests (cordicabs_tb)
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if (ENABLE_XILINX)
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find_file (INPUT_DAT_TB input.dat HINTS ${CMAKE_SOURCE_DIR}/data REQUIRED)
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if (CMAKE_VERSION VERSION_LESS 3.19.0)
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cmake_policy (SET CMP0110 OLD)
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add_test (NAME "\"Xilinx C-Simulation Testbench\"" COMMAND cordicabs_xilinx_tb
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${INPUT_DAT_TB}
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)
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else ()
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cmake_policy (SET CMP0110 NEW)
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add_test (NAME "Xilinx C-Simulation Testbench" COMMAND cordicabs_xilinx_tb ${INPUT_DAT_TB})
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endif ()
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if (XILINX_COSIM)
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set (
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XILINX_TESTLINES
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"1000"
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CACHE STRING "Number of co-simulation passes"
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)
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if (XILINX_IP)
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set (
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EXPORT_IP
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"1"
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CACHE INTERNAL "EXPORT_IP"
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)
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if (XILINX_IMPL)
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set (
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RUN_IMPL
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"1"
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CACHE INTERNAL "RUN_IMPL"
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)
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endif ()
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endif ()
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add_custom_target (
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run_hls
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COMMAND ${XILINX_HLS} ${CMAKE_SOURCE_DIR}/hls_files/cordicabs_16_4_6/script_16_4_6.tcl
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${XILINX_TESTLINES} ${EXPORT_IP} ${RUN_IMPL}
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WORKING_DIRECTORY ${CMAKE_SOURCE_DIR}/hls_files/cordicabs_16_4_6
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USES_TERMINAL
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)
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if (CMAKE_VERSION VERSION_LESS 3.190.0)
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cmake_policy (SET CMP0110 OLD)
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add_test (NAME "\"Xilinx HLS TCL Flow\"" COMMAND run_hls)
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else ()
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cmake_policy (SET CMP0110 NEW)
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add_test (NAME "Xilinx HLS TCL Flow" COMMAND run_hls)
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endif ()
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endif ()
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endif ()
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endif ()
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@ -22,6 +22,8 @@ The [Catch2](https://github.com/catchorg/Catch) test framework has been used in
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- Uses Catch v2.13.7,
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- Depends on Xilinx HLS arbitrary precision types, available as FOSS [here provided by Xilinx](https://github.com/Xilinx/HLS_arbitrary_Precision_Types) or [here patched by myself](https://github.com/DrasLorus/HLS_arbitrary_Precision_Types). Note: Xilinx also provides proprietary versions of those headers, suitable for synthesis and implementation, bundled with their products.
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A Xilinx C++ HLS testbench is also available, as well as a TCL script to run simulation, synthesis, co-simulation and IP export and implementation if wanted. Xilinx HLS v2020.2 can be directly called from CMake by the target `run_hls` if the options `ENABLE_TESTING`, `ENABLE_XILINX` and `COSIM_XILINX` are enabled. If CMake feels like black magic, It is advice to use tools like `ccmake` (NCurses terminal interface to cmake) or `cmake-gui`.
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## License and copyright
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Copyright 2022 Camille "DrasLorus" Monière.
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@ -1,9 +1,41 @@
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set VERSION [version -short]
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set SCRIPT_DIR [file normalize [file dirname [info script]]]
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set ROOT_DIR "${SCRIPT_DIR}/../.."
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set CFLAGS "-std=c++14 -Wno-unknown-pragmas -Wno-unused-label -Wall -DNDEBUG -I${ROOT_DIR}/sources"
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# if {[expr {$VERSION < 2020.1}]} {
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# error "Version less than 2020.1 is not supported."
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# }
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open_project -reset cordicabs_16_4_6
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if { [expr {$argc > 0}] } {
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set NLINES [lindex $argv 0]
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} else {
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set NLINES 10000
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}
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if { [expr {$argc > 1}] } {
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set EXPORT_IP [lindex $argv 1]
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} else {
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set EXPORT_IP 1
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}
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if { [expr {$argc > 2}] && $EXPORT_IP } {
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set RUN_IMPL [lindex $argv 2]
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} else {
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set RUN_IMPL 0
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}
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set XILINX_MAJOR [expr {int($VERSION)}]
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if {[expr {$VERSION < 2020.1}]} {
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set CFLAGS "-std=c++0x -DXILINX_MAJOR=${XILINX_MAJOR} -Wno-unknown-pragmas -Wno-unused-label -Wall -DNDEBUG -I${ROOT_DIR}/sources"
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} else {
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set CFLAGS "-std=c++14 -Wno-unknown-pragmas -Wno-unused-label -Wall -DNDEBUG -I${ROOT_DIR}/sources"
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}
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set PROJECT_NAME "cordicabs_16_4_6"
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open_project -reset ${PROJECT_NAME}
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set_top cordic_abs_16_4_6
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add_files -cflags "$CFLAGS" "${ROOT_DIR}/sources/CCordicAbs/CCordicAbs.cpp"
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add_files -cflags "$CFLAGS" "${ROOT_DIR}/sources/CCordicAbs/CCordicAbs.hpp"
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@ -11,12 +43,75 @@ add_files -cflags "$CFLAGS" "${ROOT_DIR}/sources/hls_abs/hls_abs.hpp"
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add_files -cflags "$CFLAGS" "${ROOT_DIR}/sources/top_level/top_level_cordic.cpp"
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add_files -cflags "$CFLAGS" -tb "${ROOT_DIR}/sources/top_level/top_level_cordic_tb.cpp"
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open_solution "solution_spartan7" -flow_target vivado
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set_part {xc7s100fgga484-1}
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if {[expr {$VERSION < 2020.1}]} {
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open_solution -reset "solution_spartan7"
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} else {
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open_solution -reset "solution_spartan7" -flow_target vivado
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}
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set_part {xc7s100-fgga484-1}
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create_clock -period 10 -name default
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set_clock_uncertainty 2
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#source "./cordicabs_16_4_6/solution/directives.tcl"
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set_directive_pipeline cordic_abs_16_4_6
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set_directive_interface cordic_abs_16_4_6 -mode ap_ctrl_none
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csim_design -argv "${ROOT_DIR}/data/input.dat" -clean -O
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csynth_design
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cosim_design -O -argv "${ROOT_DIR}/data/input.dat"
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export_design -format ip_catalog
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cosim_design -O -argv "${ROOT_DIR}/data/input.dat ${NLINES}"
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if { $EXPORT_IP } {
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config_export -format ip_catalog \
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-display_name "${PROJECT_NAME}" \
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-ipname "${PROJECT_NAME}_spartan7" \
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-version "0.1.${XILINX_MAJOR}"
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if { [expr {$VERSION >= 2020.1}] } {
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config_export -output "${ROOT_DIR}/hls_files/cordicabs_16_4_6/ip/${XILINX_MAJOR}_spartan7"
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}
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if { $RUN_IMPL } {
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export_design -flow impl
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} else {
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export_design
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}
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if { [expr {$VERSION < 2020.1}] } {
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set IP_FILE [glob -directory "${SCRIPT_DIR}/${PROJECT_NAME}/solution_spartan7/impl/ip" *.zip]
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file copy -force "${IP_FILE}" "${ROOT_DIR}/hls_files/cordicabs_16_4_6/ip/${XILINX_MAJOR}_spartan7.zip"
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}
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}
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close_solution
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if {[expr {$VERSION < 2020.1}]} {
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open_solution -reset "solution_genesys2"
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} else {
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open_solution -reset "solution_genesys2" -flow_target vivado
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}
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set_part {xc7k325tffg900-2}
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create_clock -period 10 -name default
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set_clock_uncertainty 2
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set_directive_pipeline cordic_abs_16_4_6
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set_directive_interface cordic_abs_16_4_6 -mode ap_ctrl_none
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csim_design -argv "${ROOT_DIR}/data/input.dat" -clean -O
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csynth_design
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cosim_design -O -argv "${ROOT_DIR}/data/input.dat ${NLINES}"
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if { $EXPORT_IP } {
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config_export -format ip_catalog \
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-display_name "${PROJECT_NAME}" \
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-ipname "${PROJECT_NAME}_genesys2" \
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-version "0.1.${XILINX_MAJOR}"
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if { [expr {$VERSION >= 2020.1}] } {
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config_export -output "${ROOT_DIR}/hls_files/cordicabs_16_4_6/ip/${XILINX_MAJOR}_genesys2"
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}
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if { $RUN_IMPL } {
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export_design -flow impl
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} else {
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export_design
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}
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if { [expr {$VERSION < 2020.1}] } {
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set IP_FILE [glob -directory "${SCRIPT_DIR}/${PROJECT_NAME}/solution_genesys2/impl/ip" *.zip]
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file copy -force "${IP_FILE}" "${ROOT_DIR}/hls_files/cordicabs_16_4_6/ip/${XILINX_MAJOR}_genesys2.zip"
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}
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}
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close_solution
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close_project
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exit 0
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@ -50,18 +50,24 @@ public:
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static constexpr const unsigned Out_I = In_I + 3;
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static constexpr const unsigned nb_stages = Tnb_stages;
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static constexpr unsigned kn_i = unsigned(kn_values[nb_stages - 1] * double(1U << 3)); // 3 bits are enough
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static constexpr unsigned kn_i = unsigned(kn_values[nb_stages - 1] * double(1U << 4)); // 4 bits are enough
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static constexpr unsigned in_scale_factor = unsigned(1U << (In_W - In_I));
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static constexpr unsigned out_scale_factor = unsigned(1U << (Out_W - Out_I));
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static constexpr int64_t scale_cordic(int64_t in) {
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return in * kn_i / 8U;
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return in * kn_i / 16U;
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}
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|
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static constexpr double scale_cordic(double in) {
|
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return in * kn_values[nb_stages - 1];
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}
|
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|
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static constexpr ap_uint<Out_W> scale_cordic(ap_uint<Out_W> in) {
|
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return ap_uint<Out_W>(ap_uint<Out_W+4>(in * ap_uint<4>(kn_i)) >> 4U);
|
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}
|
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|
||||
|
||||
#if !defined (XILINX_MAJOR) || XILINX_MAJOR >= 2020
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static constexpr ap_uint<Out_W> process(ap_int<In_W> re_in, ap_int<In_W> im_in) {
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ap_int<Out_W> A[nb_stages + 1];
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ap_int<Out_W> B[nb_stages + 1];
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@ -88,6 +94,7 @@ public:
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|
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return ap_uint<Out_W>(A[nb_stages]);
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}
|
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#endif
|
||||
|
||||
#if !defined(__SYNTHESIS__) && defined(SOFTWARE)
|
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static constexpr uint64_t process(int64_t re_in, int64_t im_in) {
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|||
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@ -19,11 +19,11 @@
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||||
#include "top_level_cordic.hpp"
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#include "hls_stream.h"
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#if !defined (XILINX_MAJOR) || XILINX_MAJOR >= 2020
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|
||||
void cordic_abs_16_4_6(
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ap_int<cordic_abs_t::In_W> re_in,
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ap_int<cordic_abs_t::In_W> im_in,
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ap_int<cordic_abs_t::In_W> re_in,
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ap_int<cordic_abs_t::In_W> im_in,
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ap_uint<cordic_abs_t::Out_W> & module_out) {
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|
||||
static constexpr const cordic_abs_t cordic_abs {};
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|
|
@ -35,3 +35,51 @@ void cordic_abs_16_4_6(
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|
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module_out = m;
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||||
}
|
||||
|
||||
#else
|
||||
|
||||
constexpr unsigned In_W = cordic_abs_t::In_W;
|
||||
constexpr unsigned Out_W = cordic_abs_t::Out_W;
|
||||
constexpr unsigned nb_stages = cordic_abs_t::nb_stages;
|
||||
|
||||
static ap_uint<Out_W> process(ap_int<In_W> re_in, ap_int<In_W> im_in) {
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||||
ap_int<Out_W> A[nb_stages + 1];
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||||
ap_int<Out_W> B[nb_stages + 1];
|
||||
|
||||
A[0] = hls_abs<false>::abs(re_in);
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||||
B[0] = hls_abs<false>::abs(im_in);
|
||||
|
||||
for (uint16_t u = 0; u < nb_stages; u++) {
|
||||
const bool sign_B = B[u] > 0;
|
||||
|
||||
const ap_int<Out_W> step_A = B[u] >> u;
|
||||
const ap_int<Out_W> step_B = A[u] >> u;
|
||||
|
||||
const ap_int<Out_W> tmp_B = sign_B
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||||
? ap_int<Out_W>(B[u] - step_B)
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: ap_int<Out_W>(B[u] + step_B);
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||||
const ap_int<Out_W> tmp_A = sign_B
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? ap_int<Out_W>(A[u] + step_A)
|
||||
: ap_int<Out_W>(A[u] - step_A);
|
||||
|
||||
A[u + 1] = tmp_A;
|
||||
B[u + 1] = tmp_B;
|
||||
}
|
||||
|
||||
return ap_uint<Out_W>(A[nb_stages]);
|
||||
}
|
||||
|
||||
void cordic_abs_16_4_6(
|
||||
ap_int<cordic_abs_t::In_W> re_in,
|
||||
ap_int<cordic_abs_t::In_W> im_in,
|
||||
ap_uint<cordic_abs_t::Out_W> & module_out) {
|
||||
|
||||
const ap_int<cordic_abs_t::In_W> x = re_in;
|
||||
const ap_int<cordic_abs_t::In_W> y = im_in;
|
||||
|
||||
const ap_uint<cordic_abs_t::Out_W> m = process(x, y);
|
||||
|
||||
module_out = m;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -40,17 +40,21 @@ int main(int argc, char ** argv) {
|
|||
|
||||
string input_fn = "../data/input.dat"; // _8_14_4_17_5_19_7_12
|
||||
|
||||
if (argc == 2) {
|
||||
if (argc > 1) {
|
||||
input_fn = string(argv[1]);
|
||||
}
|
||||
|
||||
constexpr unsigned n_lines = 100;
|
||||
constexpr unsigned max_lines = 10000;
|
||||
unsigned n_lines = max_lines;
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if (argc > 2) {
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n_lines = unsigned(std::stoi(string(argv[2])));
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}
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ap_int<cordic_abs_t::In_W> re_values_in[n_lines];
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ap_int<cordic_abs_t::In_W> im_values_in[n_lines];
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ap_uint<cordic_abs_t::Out_W> values_out[n_lines];
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ap_int<cordic_abs_t::In_W> re_values_in[max_lines];
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ap_int<cordic_abs_t::In_W> im_values_in[max_lines];
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ap_uint<cordic_abs_t::Out_W> values_out[max_lines];
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double results[n_lines];
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double results[max_lines];
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FILE * INPUT = fopen(input_fn.c_str(), "r");
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@ -81,7 +85,6 @@ int main(int argc, char ** argv) {
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cordic_abs_16_4_6(re_values_in[iter], im_values_in[iter], values_out[iter]);
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// Display the results
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// cout << "Series " << iter;
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// cout << " Outcome: ";
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@ -91,7 +94,7 @@ int main(int argc, char ** argv) {
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// << cordic_abs_t::scale_cordic(values_out[iter].to_double()) / cordic_abs_t::out_scale_factor << " "
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// << results[iter] << std::endl;
|
||||
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const double dbl_res = cordic_abs_t::scale_cordic(values_out[iter].to_double() ) / cordic_abs_t::out_scale_factor;
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const double dbl_res = cordic_abs_t::scale_cordic(values_out[iter].to_double()) / cordic_abs_t::out_scale_factor;
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||||
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||||
if (std::abs(dbl_res - results[iter]) > abs_margin) {
|
||||
counted_errors++;
|
||||
|
|
|
|||
Loading…
Reference in a new issue