mirror of
https://github.com/DrasLorus/CORDIC_Abs_APFX.git
synced 2024-11-12 16:13:16 +01:00
Enable support of GNU v4.6 and (consequently) of Vivado HLS 2019.1
- Also disable TCL unit COSIM test. Can be enable by turning 'true' to false in the CMakeLists, - v4.6 doesn't support C++14, nor some C++11, so some hacky ways have been found. Unit test has been updated but still works and coverage is good (94%, the 6% beeing exeption handling, unrelevant in HLS).
This commit is contained in:
DrasLorus
parent
7844c3bdd1
commit
d9f80fc165
GPG key ID:
188DD5B072181C0F
5 changed files with 162 additions and 180 deletions
125
CMakeLists.txt
125
CMakeLists.txt
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@ -25,15 +25,23 @@ project (
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)
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if ((CMAKE_CXX_COMPILER_ID STREQUAL "GNU") AND (CMAKE_CXX_COMPILER_VERSION VERSION_LESS 6.2))
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message (
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FATAL_ERROR
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"This project require a GNU compiler version greater than 6.2."
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"\nNote: If you tried to use g++-4.6.3 as provided by Xilinx Vivado v2019.1, use directly the TCL script "
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"in the folder `hls_files/cordicabs_16_4_6`."
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)
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# message ( FATAL_ERROR "This project require a GNU compiler version greater than 6.2." "\nNote:
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# If you tried to use g++-4.6.3 as provided by Xilinx Vivado v2019.1, use directly the TCL script
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# " "in the folder `hls_files/cordicabs_16_4_6`." )
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set (IS_GNU_LEGACY ON)
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else ()
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set (IS_GNU_LEGACY OFF)
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endif ()
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set (CMAKE_CXX_STANDARD 14)
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if (IS_GNU_LEGACY)
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set (CMAKE_CXX_STANDARD 11)
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message (
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WARNING
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"An old GNU compiler is currently used, Catch2, C++14 and advanced C++11 features are disabled."
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)
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else ()
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set (CMAKE_CXX_STANDARD 14)
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endif ()
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set (CMAKE_CXX_STANDARD_REQUIRED ON)
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set (CMAKE_CXX_EXTENSIONS OFF)
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@ -63,6 +71,7 @@ option (ENABLE_SOFTWARE
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)
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option (PEDANTIC "use -Wall and -pedantic." ON)
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option (ENABLE_GCOV "use GCOV and LCOV to assess code coverage." OFF)
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# ##################################################################################################
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@ -70,6 +79,16 @@ if (PEDANTIC)
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add_compile_options (-Wall -pedantic)
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endif ()
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if (ENABLE_GCOV)
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add_compile_options (
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-O0
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-fprofile-arcs
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-ftest-coverage
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-fprofile-abs-path
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)
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add_link_options (-lgcov --coverage)
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endif ()
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if (EXPORT_COMMANDS)
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set (CMAKE_EXPORT_COMPILE_COMMANDS ON)
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endif ()
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@ -82,7 +101,7 @@ if (ENABLE_XILINX)
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)
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set (
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XILINX_VER
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"2020.2"
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"2019.1"
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CACHE STRING "Xilinx software version to use."
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)
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@ -96,9 +115,15 @@ if (ENABLE_XILINX)
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XILINX_HLS vitis_hls HINTS ${XILINX_HOME}/Vitis_HLS/${XILINX_VER}/bin NO_CACHE REQUIRED
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)
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else ()
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message (
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FATAL_ERROR
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"Xilinx versions less than 2020.1 are not supported due to the outdated compiler version in use"
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# message ( FATAL_ERROR "Xilinx versions less than 2020.1 are not supported due to the outdated
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# compiler version in use" )
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set (
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AP_INCLUDE_DIR
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${XILINX_HOME}/Vivado/${XILINX_VER}/include
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CACHE INTERNAL "Path to Xilinx includes" FORCE
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)
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find_program (
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XILINX_HLS vivado_hls HINTS ${XILINX_HOME}/Vivado/${XILINX_VER}/bin NO_CACHE REQUIRED
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)
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endif ()
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message (STATUS "AP headers must lie under ${AP_INCLUDE_DIR}")
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@ -144,24 +169,30 @@ if (ENABLE_XILINX)
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endif ()
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if (ENABLE_TESTING)
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find_package (Catch2 REQUIRED)
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add_library (catch_common_${PROJECT_NAME} OBJECT sources/tb/main_catch2.cpp)
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target_link_libraries (catch_common_${PROJECT_NAME} PUBLIC Catch2::Catch2)
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add_executable (cordicabs_tb sources/tb/cordicabs_tb.cpp)
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target_link_libraries (cordicabs_tb catch_common_${PROJECT_NAME} cordicabs)
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include (CTest)
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include (Catch)
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catch_discover_tests (cordicabs_tb WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}/data)
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if (CMAKE_VERSION VERSION_GREATER_EQUAL 3.19.0)
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cmake_policy (SET CMP0110 NEW)
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endif ()
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if (NOT IS_GNU_LEGACY)
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find_package (Catch2 REQUIRED)
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add_library (catch_common_${PROJECT_NAME} OBJECT sources/tb/main_catch2.cpp)
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target_link_libraries (catch_common_${PROJECT_NAME} PUBLIC Catch2::Catch2)
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add_executable (cordicabs_tb sources/tb/cordicabs_tb.cpp)
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target_link_libraries (cordicabs_tb catch_common_${PROJECT_NAME} cordicabs)
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include (Catch)
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catch_discover_tests (cordicabs_tb WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}/data)
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endif ()
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if (ENABLE_XILINX)
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find_file (INPUT_DAT_TB input.dat HINTS data NO_CACHE REQUIRED)
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if (CMAKE_VERSION VERSION_LESS 3.19.0)
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set (TEST_NAME "\"Xilinx C-Simulation Testbench CordicAbs\"")
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else ()
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cmake_policy (SET CMP0110 NEW)
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set (TEST_NAME "Xilinx C-Simulation Testbench CordicAbs")
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endif ()
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add_test (NAME ${TEST_NAME} COMMAND cordicabs_xilinx_tb ${INPUT_DAT_TB})
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@ -169,7 +200,7 @@ if (ENABLE_TESTING)
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if (XILINX_COSIM)
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set (
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XILINX_TESTLINES
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"1000"
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"10000"
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CACHE STRING "Number of co-simulation passes"
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)
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@ -179,38 +210,40 @@ if (ENABLE_TESTING)
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"1"
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CACHE INTERNAL "EXPORT_IP"
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)
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if (XILINX_IMPL)
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set (
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RUN_IMPL
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"1"
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CACHE INTERNAL "RUN_IMPL"
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)
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endif ()
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else ()
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unset (EXPORT_IP CACHE)
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endif ()
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if (XILINX_IMPL)
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set (
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RUN_IMPL
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"1"
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CACHE INTERNAL "RUN_IMPL"
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)
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else ()
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unset (RUN_IMPL CACHE)
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endif ()
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add_custom_target (
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run_hls
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COMMAND ${XILINX_HLS} ${CMAKE_SOURCE_DIR}/hls_files/cordicabs_16_4_6/script_16_4_6.tcl
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${XILINX_TESTLINES} ${EXPORT_IP} ${RUN_IMPL}
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WORKING_DIRECTORY ${CMAKE_SOURCE_DIR}/hls_files/cordicabs_16_4_6
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COMMAND
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${XILINX_HLS} ${CMAKE_CURRENT_SOURCE_DIR}/hls_files/cordicabs_16_4_6/script_16_4_6.tcl
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${XILINX_TESTLINES} ${EXPORT_IP} ${RUN_IMPL}
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WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}/hls_files/cordicabs_16_4_6
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USES_TERMINAL
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)
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if (CMAKE_VERSION VERSION_LESS 3.19.0)
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add_test (
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NAME "\"Xilinx HLS TCL Flow\""
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COMMAND ${XILINX_HLS} ${CMAKE_SOURCE_DIR}/hls_files/cordicabs_16_4_6/script_16_4_6.tcl
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${XILINX_TESTLINES} 0 0
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WORKING_DIRECTORY ${CMAKE_SOURCE_DIR}/hls_files/cordicabs_16_4_6
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)
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set (TEST_NAME "\"Xilinx HLS TCL Flow\"")
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else ()
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cmake_policy (SET CMP0110 NEW)
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add_test (
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NAME "Xilinx HLS TCL Flow"
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COMMAND ${XILINX_HLS} ${CMAKE_SOURCE_DIR}/hls_files/cordicabs_16_4_6/script_16_4_6.tcl
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${XILINX_TESTLINES} 0 0
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WORKING_DIRECTORY ${CMAKE_SOURCE_DIR}/hls_files/cordicabs_16_4_6
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)
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set (TEST_NAME "Xilinx HLS TCL Flow")
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endif ()
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add_test (
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${TEST_NAME}
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COMMAND
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${XILINX_HLS} ${CMAKE_CURRENT_SOURCE_DIR}/hls_files/cordicabs_16_4_6/script_16_4_6.tcl
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${XILINX_TESTLINES} 0 0
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WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}/hls_files/cordicabs_16_4_6
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)
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set_property (TEST ${TEST_NAME} PROPERTY DISABLED TRUE)
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endif ()
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endif ()
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endif ()
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@ -16,7 +16,7 @@ if { [expr {$argc > 0}] } {
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if { [expr {$argc > 1}] } {
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set EXPORT_IP [lindex $argv 1]
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} else {
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set EXPORT_IP 1
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set EXPORT_IP 0
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}
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if { [expr {$argc > 2}] && $EXPORT_IP } {
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@ -30,7 +30,7 @@ set XILINX_MAJOR [expr {int($VERSION)}]
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if {[expr {$VERSION < 2020.1}]} {
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set CFLAGS "-std=c++0x -DXILINX_MAJOR=${XILINX_MAJOR} -Wno-unknown-pragmas -Wno-unused-label -Wall -DNDEBUG -I${ROOT_DIR}/sources"
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} else {
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set CFLAGS "-std=c++14 -Wno-unknown-pragmas -Wno-unused-label -Wall -DNDEBUG -I${ROOT_DIR}/sources"
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set CFLAGS "-std=c++14 -DXILINX_MAJOR=${XILINX_MAJOR} -Wno-unknown-pragmas -Wno-unused-label -Wall -DNDEBUG -I${ROOT_DIR}/sources"
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}
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set PROJECT_NAME "cordicabs_16_4_6"
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@ -43,75 +43,56 @@ add_files -cflags "$CFLAGS" "${ROOT_DIR}/sources/hls_abs/hls_abs.hpp"
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add_files -cflags "$CFLAGS" "${ROOT_DIR}/sources/top_level/top_level_cordic.cpp"
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add_files -cflags "$CFLAGS" -tb "${ROOT_DIR}/sources/top_level/top_level_cordic_tb.cpp"
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if {[expr {$VERSION < 2020.1}]} {
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open_solution -reset "solution_spartan7"
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} else {
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open_solution -reset "solution_spartan7" -flow_target vivado
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}
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set_part {xc7s100-fgga484-1}
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create_clock -period 10 -name default
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set_clock_uncertainty 2
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set_directive_pipeline cordic_abs_16_4_6
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set_directive_interface cordic_abs_16_4_6 -mode ap_ctrl_none
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csim_design -argv "${ROOT_DIR}/data/input.dat" -clean -O
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csynth_design
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cosim_design -O -argv "${ROOT_DIR}/data/input.dat ${NLINES}"
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if { $EXPORT_IP } {
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config_export -format ip_catalog \
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-display_name "${PROJECT_NAME}" \
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-ipname "${PROJECT_NAME}_spartan7" \
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-version "0.1.${XILINX_MAJOR}"
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||||
if { [expr {$VERSION >= 2020.1}] } {
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config_export -output "${ROOT_DIR}/hls_files/cordicabs_16_4_6/ip/${XILINX_MAJOR}_spartan7"
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set targets [ dict create spartan7 {xc7s100-fgga484-1} genesys2 {xc7k325tffg900-2} ]
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foreach target { spartan7 genesys2 } {
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if {[expr {$VERSION < 2020.1}]} {
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open_solution -reset "solution_${target}"
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} else {
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open_solution -reset "solution_${target}" -flow_target vivado
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||||
}
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||||
set_part [ dict get $targets $target ]
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create_clock -period 10 -name default
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set_clock_uncertainty 2
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set_directive_pipeline cordic_abs_16_4_6
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set_directive_interface cordic_abs_16_4_6 -mode ap_ctrl_none
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||||
csim_design -argv "${ROOT_DIR}/data/input.dat" -clean -O
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csynth_design
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cosim_design -O -argv "${ROOT_DIR}/data/input.dat ${NLINES}"
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config_export -format ip_catalog \
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-display_name "${PROJECT_NAME}" \
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-ipname "${PROJECT_NAME}_${target}" \
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-version "0.1.${XILINX_MAJOR}" \
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-vivado_optimization_level 2 \
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-vivado_phys_opt route
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|
||||
if { $EXPORT_IP } {
|
||||
if [ expr {! [ file isdirectory "${ROOT_DIR}/ip" ] } ] {
|
||||
if { [ file exists "${ROOT_DIR}/ip" ] } {
|
||||
file remove "${ROOT_DIR}/ip"
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||||
}
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||||
file mkdir "${ROOT_DIR}/ip"
|
||||
}
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||||
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||||
if { [expr {$VERSION >= 2020.1}] } {
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||||
export_design -output "${ROOT_DIR}/hls_files/cordicabs_16_4_6/ip/${XILINX_MAJOR}_${target}"
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||||
} else {
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||||
export_design
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set IP_FILE [glob -directory "${SCRIPT_DIR}/${PROJECT_NAME}/solution_${target}/impl/ip" *.zip]
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||||
file copy -force "${IP_FILE}" "${ROOT_DIR}/hls_files/cordicabs_16_4_6/ip/${XILINX_MAJOR}_${target}.zip"
|
||||
}
|
||||
}
|
||||
|
||||
if { $RUN_IMPL } {
|
||||
export_design -flow impl
|
||||
} else {
|
||||
export_design
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||||
}
|
||||
if { [expr {$VERSION < 2020.1}] } {
|
||||
set IP_FILE [glob -directory "${SCRIPT_DIR}/${PROJECT_NAME}/solution_spartan7/impl/ip" *.zip]
|
||||
file copy -force "${IP_FILE}" "${ROOT_DIR}/hls_files/cordicabs_16_4_6/ip/${XILINX_MAJOR}_spartan7.zip"
|
||||
}
|
||||
|
||||
close_solution
|
||||
}
|
||||
|
||||
close_solution
|
||||
|
||||
if {[expr {$VERSION < 2020.1}]} {
|
||||
open_solution -reset "solution_genesys2"
|
||||
} else {
|
||||
open_solution -reset "solution_genesys2" -flow_target vivado
|
||||
}
|
||||
set_part {xc7k325tffg900-2}
|
||||
create_clock -period 10 -name default
|
||||
set_clock_uncertainty 2
|
||||
set_directive_pipeline cordic_abs_16_4_6
|
||||
set_directive_interface cordic_abs_16_4_6 -mode ap_ctrl_none
|
||||
csim_design -argv "${ROOT_DIR}/data/input.dat" -clean -O
|
||||
csynth_design
|
||||
cosim_design -O -argv "${ROOT_DIR}/data/input.dat ${NLINES}"
|
||||
|
||||
if { $EXPORT_IP } {
|
||||
config_export -format ip_catalog \
|
||||
-display_name "${PROJECT_NAME}" \
|
||||
-ipname "${PROJECT_NAME}_genesys2" \
|
||||
-version "0.1.${XILINX_MAJOR}"
|
||||
if { [expr {$VERSION >= 2020.1}] } {
|
||||
config_export -output "${ROOT_DIR}/hls_files/cordicabs_16_4_6/ip/${XILINX_MAJOR}_genesys2"
|
||||
}
|
||||
if { $RUN_IMPL } {
|
||||
export_design -flow impl
|
||||
} else {
|
||||
export_design
|
||||
}
|
||||
if { [expr {$VERSION < 2020.1}] } {
|
||||
set IP_FILE [glob -directory "${SCRIPT_DIR}/${PROJECT_NAME}/solution_genesys2/impl/ip" *.zip]
|
||||
file copy -force "${IP_FILE}" "${ROOT_DIR}/hls_files/cordicabs_16_4_6/ip/${XILINX_MAJOR}_genesys2.zip"
|
||||
}
|
||||
}
|
||||
|
||||
close_solution
|
||||
close_project
|
||||
|
||||
exit 0
|
||||
|
|
|
|||
|
|
@ -37,20 +37,36 @@
|
|||
|
||||
#define cst_abs(x) (x > 0 ? x : -x)
|
||||
|
||||
#if __cplusplus < 201402L && XILINX_MAJOR <= 2019
|
||||
#ifndef kn_values
|
||||
const double kn_values_define[7] = {
|
||||
0.70710678118655, 0.632455532033680, 0.613571991077900,
|
||||
0.608833912517750, 0.607648256256170, 0.607351770141300, 0.607277644093530};
|
||||
#define kn_values kn_values_define
|
||||
#define kn_i unsigned(kn_values[Tnb_stages - 1] * double(1U << 4))
|
||||
#endif
|
||||
|
||||
#define OWN_CONSTEXPR
|
||||
#else
|
||||
#define OWN_CONSTEXPR constexpr
|
||||
#endif
|
||||
|
||||
template <unsigned TIn_W, unsigned TIn_I, unsigned Tnb_stages>
|
||||
class CCordicAbs {
|
||||
public:
|
||||
#if __cplusplus >= 201402L || XILINX_MAJOR > 2019
|
||||
static constexpr double kn_values[7] = {
|
||||
0.70710678118655, 0.632455532033680, 0.613571991077900,
|
||||
0.608833912517750, 0.607648256256170, 0.607351770141300, 0.607277644093530};
|
||||
|
||||
static constexpr const unsigned In_W = TIn_W;
|
||||
static constexpr const unsigned In_I = TIn_I;
|
||||
static constexpr const unsigned Out_W = In_W + 2;
|
||||
static constexpr const unsigned Out_I = In_I + 2;
|
||||
static constexpr const unsigned nb_stages = Tnb_stages;
|
||||
static constexpr unsigned kn_i = unsigned(kn_values[Tnb_stages - 1] * double(1U << 4)); // 4 bits are enough
|
||||
#endif
|
||||
static constexpr unsigned In_W = TIn_W;
|
||||
static constexpr unsigned In_I = TIn_I;
|
||||
static constexpr unsigned Out_W = In_W + 2;
|
||||
static constexpr unsigned Out_I = In_I + 2;
|
||||
static constexpr unsigned nb_stages = Tnb_stages;
|
||||
|
||||
static constexpr unsigned kn_i = unsigned(kn_values[nb_stages - 1] * double(1U << 4)); // 4 bits are enough
|
||||
static constexpr unsigned in_scale_factor = unsigned(1U << (In_W - In_I));
|
||||
static constexpr unsigned out_scale_factor = unsigned(1U << (Out_W - Out_I));
|
||||
|
||||
|
|
@ -66,8 +82,7 @@ public:
|
|||
return ap_uint<Out_W>(ap_uint<Out_W + 4>(in * ap_uint<4>(kn_i)) >> 4U);
|
||||
}
|
||||
|
||||
#if !defined(XILINX_MAJOR) || XILINX_MAJOR >= 2020
|
||||
static constexpr ap_uint<Out_W> process(ap_int<In_W> re_in, ap_int<In_W> im_in) {
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static OWN_CONSTEXPR ap_uint<Out_W> process(ap_int<In_W> re_in, ap_int<In_W> im_in) {
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ap_int<Out_W> A[nb_stages + 1];
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ap_int<Out_W> B[nb_stages + 1];
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@ -93,9 +108,8 @@ public:
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return ap_uint<Out_W>(A[nb_stages]);
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}
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#endif
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#if !defined(__SYNTHESIS__) && defined(SOFTWARE)
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#if !defined(__SYNTHESIS__) && defined(SOFTWARE) && __cplusplus >= 201402L
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static constexpr uint64_t process(int64_t re_in, int64_t im_in) {
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const int64_t re_x = re_in;
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|
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@ -19,67 +19,17 @@
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#include "top_level_cordic.hpp"
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#if !defined(XILINX_MAJOR) || XILINX_MAJOR >= 2020
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void cordic_abs_16_4_6(
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ap_int<cordic_abs_t::In_W> re_in,
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ap_int<cordic_abs_t::In_W> im_in,
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ap_uint<cordic_abs_t::Out_W> & module_out) {
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static constexpr const cordic_abs_t cordic_abs {};
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// static constexpr const cordic_abs_t cordic_abs {};
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const ap_int<cordic_abs_t::In_W> x = re_in;
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const ap_int<cordic_abs_t::In_W> y = im_in;
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const ap_uint<cordic_abs_t::Out_W> m = cordic_abs.process(x, y);
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const ap_uint<cordic_abs_t::Out_W> m = cordic_abs_t::process(x, y);
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module_out = m;
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}
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#else
|
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constexpr unsigned In_W = cordic_abs_t::In_W;
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constexpr unsigned Out_W = cordic_abs_t::Out_W;
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constexpr unsigned nb_stages = cordic_abs_t::nb_stages;
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|
||||
static ap_uint<Out_W> process(ap_int<In_W> re_in, ap_int<In_W> im_in) {
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ap_int<Out_W> A[nb_stages + 1];
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||||
ap_int<Out_W> B[nb_stages + 1];
|
||||
|
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A[0] = hls_abs<false>::abs(re_in);
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B[0] = hls_abs<false>::abs(im_in);
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for (uint16_t u = 0; u < nb_stages; u++) {
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const bool sign_B = B[u] > 0;
|
||||
|
||||
const ap_int<Out_W> step_A = B[u] >> u;
|
||||
const ap_int<Out_W> step_B = A[u] >> u;
|
||||
|
||||
const ap_int<Out_W> tmp_B = sign_B
|
||||
? ap_int<Out_W>(B[u] - step_B)
|
||||
: ap_int<Out_W>(B[u] + step_B);
|
||||
const ap_int<Out_W> tmp_A = sign_B
|
||||
? ap_int<Out_W>(A[u] + step_A)
|
||||
: ap_int<Out_W>(A[u] - step_A);
|
||||
|
||||
A[u + 1] = tmp_A;
|
||||
B[u + 1] = tmp_B;
|
||||
}
|
||||
|
||||
return ap_uint<Out_W>(A[nb_stages]);
|
||||
}
|
||||
|
||||
void cordic_abs_16_4_6(
|
||||
ap_int<cordic_abs_t::In_W> re_in,
|
||||
ap_int<cordic_abs_t::In_W> im_in,
|
||||
ap_uint<cordic_abs_t::Out_W> & module_out) {
|
||||
|
||||
const ap_int<cordic_abs_t::In_W> x = re_in;
|
||||
const ap_int<cordic_abs_t::In_W> y = im_in;
|
||||
|
||||
const ap_uint<cordic_abs_t::Out_W> m = process(x, y);
|
||||
|
||||
module_out = m;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -44,10 +44,10 @@ int main(int argc, char ** argv) {
|
|||
input_fn = string(argv[1]);
|
||||
}
|
||||
|
||||
constexpr unsigned max_lines = 10000;
|
||||
constexpr unsigned max_lines = 100000;
|
||||
unsigned n_lines = max_lines;
|
||||
if (argc > 2) {
|
||||
n_lines = unsigned(std::stoi(string(argv[2])));
|
||||
n_lines = std::min(unsigned(std::stoi(string(argv[2]))), max_lines);
|
||||
}
|
||||
|
||||
ap_int<cordic_abs_t::In_W> re_values_in[max_lines];
|
||||
|
|
@ -57,6 +57,10 @@ int main(int argc, char ** argv) {
|
|||
double results[max_lines];
|
||||
|
||||
FILE * INPUT = fopen(input_fn.c_str(), "r");
|
||||
if (!bool(INPUT)) {
|
||||
perror("Can't open input file");
|
||||
exit(EXIT_FAILURE);
|
||||
}
|
||||
|
||||
// Init test vector
|
||||
for (unsigned i = 0; i < n_lines; i++) {
|
||||
|
|
@ -73,7 +77,7 @@ int main(int argc, char ** argv) {
|
|||
fclose(INPUT);
|
||||
|
||||
// Save the results to a file
|
||||
// ofstream outfile("results.dat");
|
||||
ofstream outfile("results.dat");
|
||||
|
||||
constexpr double abs_margin = double(1 << (cordic_abs_t::Out_I - 1)) * 2. / 100.;
|
||||
|
||||
|
|
@ -89,10 +93,10 @@ int main(int argc, char ** argv) {
|
|||
// cout << "Series " << iter;
|
||||
// cout << " Outcome: ";
|
||||
|
||||
// outfile << re_values_in[iter].to_double() / cordic_abs_t::in_scale_factor << " "
|
||||
// << im_values_in[iter].to_double() / cordic_abs_t::in_scale_factor << " "
|
||||
// << cordic_abs_t::scale_cordic(values_out[iter].to_double()) / cordic_abs_t::out_scale_factor << " "
|
||||
// << results[iter] << std::endl;
|
||||
outfile << re_values_in[iter].to_double() / cordic_abs_t::in_scale_factor << " "
|
||||
<< im_values_in[iter].to_double() / cordic_abs_t::in_scale_factor << " "
|
||||
<< cordic_abs_t::scale_cordic(values_out[iter].to_double()) / cordic_abs_t::out_scale_factor << " "
|
||||
<< results[iter] << std::endl;
|
||||
|
||||
const double dbl_res = cordic_abs_t::scale_cordic(values_out[iter].to_double()) / cordic_abs_t::out_scale_factor;
|
||||
|
||||
|
|
@ -105,7 +109,7 @@ int main(int argc, char ** argv) {
|
|||
}
|
||||
}
|
||||
}
|
||||
// outfile.close();
|
||||
outfile.close();
|
||||
|
||||
printf("RESULT: %s!\n", counted_errors == 0 ? "SUCCESS" : "FAILURE");
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue