From 75ccdc73c8b4b36534566ac903d630504bd65b8d Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Camille=20Moni=C3=A8re?= <camillemvdd@gmail.com>
Date: Wed, 26 Jan 2022 12:21:48 +0100
Subject: [PATCH] Fixes include/etc/ap_private.h and update copyright notice

- The method `set_bits` was missing, causing compilation failures when
  using bits_to_fixed method.
- The copyright of the concerned file has been updated.
---
 README.MD                | 12 +++++++++---
 include/etc/ap_private.h |  8 ++++++++
 2 files changed, 17 insertions(+), 3 deletions(-)

diff --git a/README.MD b/README.MD
index 7849c29..662e999 100644
--- a/README.MD
+++ b/README.MD
@@ -1,13 +1,16 @@
 # HLS Arbitrary Precision Types Library
 
-This repo provides simulation code of HLS Arbitrary Precision Types.
+This repository provides simulation code of HLS Arbitrary Precision Types.
 
-The code is based from headers shipped with Vivado,
+The code is based from headers shipped with Vivado (*in 2019...*),
 but due to absence of synthesis support **it should not be used in an HLS project targeting FPGA**.
 
+For synthesis, the repository owner (A.K.A [DrasLorus](https://github.com/DrasLorus)) strongly recommends the use of Xilinx® provided headers, which are *unfortunately* proprietary software.
+
 ## Compatibility
 
-Tested with g++ (GCC) 6.2.0 on x86_64 GNU/Linux.
+- *(Legacy)* Tested with g++ (GCC) 6.2.0 on x86_64 GNU/Linux.
+- Tested with clang (LLVM) 13.0.0 and g++ (GCC) 11.1.0 on x86_64 GNU/Linux.
 
 ## Usage
 
@@ -29,6 +32,9 @@ $
 
 Copyright 2011-2019 Xilinx, Inc.
 
+Copyright 2022 DrasLorus.
+*Note*: Only [ap_private header](./include/etc/ap_private.h) has been modified by myself, copyright have thus been amended in place.
+
 Licensed under the Apache License, Version 2.0 (the "License");
 you may not use this file except in compliance with the License.
 You may obtain a copy of the License at
diff --git a/include/etc/ap_private.h b/include/etc/ap_private.h
index 0c29a0a..cfb9ac9 100644
--- a/include/etc/ap_private.h
+++ b/include/etc/ap_private.h
@@ -1,5 +1,6 @@
 /*
  * Copyright 2011-2019 Xilinx, Inc.
+ * Copyright 2022 DrasLorus.
  *
  * Licensed under the Apache License, Version 2.0 (the "License");
  * you may not use this file except in compliance with the License.
@@ -2347,6 +2348,13 @@ ASSIGN_OP_FROM_INT(double)
     v ? set(i) : clear(i);
   }
 
+  // Copyright 2022 DrasLorus
+  // Set a range of bits
+  INLINE void set_bits(ap_ulong bv) {
+    assert(((bv & ((1u << _AP_W) - 1U)) == bv) && "Attempting to write bit beyond MSB");
+    VAL = bv;
+  }
+
   // Set the ith bit into v
   INLINE void set_bit(int i, bool v) {
     assert(i >= 0 && "Attempting to write bit with negative index");