mirror of
https://github.com/DrasLorus/HLS_Byte_Serializer.git
synced 2024-07-06 15:35:18 +02:00
0d6f4fc08c
- Fix converters when type is signed - Force interface type as pragma as TCL directives on template is nearly impossible.
156 lines
5.9 KiB
Tcl
156 lines
5.9 KiB
Tcl
#
|
|
# Copyright or © or Copr. Université de Bretagne-Sud, Lab-STICC, Bordeaux-INP, IMS
|
|
# Contributor(s) : Camille Monière (2022)
|
|
#
|
|
# camille.moniere@univ-ubs.fr, camille.moniere@ims-bordeaux.fr
|
|
#
|
|
# This software is a computer program whose purpose is to simulate and implement C-type
|
|
# to bytes FPGA IPs.
|
|
#
|
|
# This software is governed by the CeCILL-B license under French law and
|
|
# abiding by the rules of distribution of free software. You can use,
|
|
# modify and/ or redistribute the software under the terms of the CeCILL-B
|
|
# license as circulated by CEA, CNRS and INRIA at the following URL
|
|
# "http://www.cecill.info".
|
|
#
|
|
# As a counterpart to the access to the source code and rights to copy,
|
|
# modify and redistribute granted by the license, users are provided only
|
|
# with a limited warranty and the software's author, the holder of the
|
|
# economic rights, and the successive licensors have only limited
|
|
# liability.
|
|
#
|
|
# In this respect, the user's attention is drawn to the risks associated
|
|
# with loading, using, modifying and/or developing or reproducing the
|
|
# software by the user in light of its specific status of free software,
|
|
# that may mean that it is complicated to manipulate, and that also
|
|
# therefore means that it is reserved for developers and experienced
|
|
# professionals having in-depth computer knowledge. Users are therefore
|
|
# encouraged to load and test the software's suitability as regards their
|
|
# requirements in conditions enabling the security of their systems and/or
|
|
# data to be ensured and, more generally, to use and operate it in the
|
|
# same conditions as regards security.
|
|
#
|
|
# The fact that you are presently reading this means that you have had
|
|
# knowledge of the CeCILL-B license and that you accept its terms.
|
|
#
|
|
|
|
set SCRIPT_DIR [file normalize [file dirname [info script]]]
|
|
set ROOT_DIR [file normalize "${SCRIPT_DIR}/../.."]
|
|
|
|
set VERSION [version -short]
|
|
set XILINX_MAJOR [expr {int($VERSION)}]
|
|
|
|
set cnt 0
|
|
if { [expr {$argc > 0}] } {
|
|
set argp 0
|
|
while { $argp < $argc } {
|
|
set curr [lindex $argv $argp]
|
|
if { [string index $curr 0] != "-" } {
|
|
if { $cnt == 0 } {
|
|
set NLINES $curr
|
|
set cnt [expr { $cnt + 1 }]
|
|
} elseif { $cnt == 1 } {
|
|
set EXPORT_IP $curr
|
|
set cnt [expr { $cnt + 1 }]
|
|
} elseif { $cnt == 2 } {
|
|
set RUN_IMPL $curr
|
|
set cnt [expr { $cnt + 1 }]
|
|
}
|
|
}
|
|
set argp [ expr { $argp + 1 } ]
|
|
}
|
|
}
|
|
|
|
if { $cnt < 1 } {
|
|
set NLINES 10000
|
|
set EXPORT_IP 0
|
|
set RUN_IMPL 0
|
|
} elseif { $cnt < 2 } {
|
|
set EXPORT_IP 0
|
|
set RUN_IMPL 0
|
|
} elseif { $cnt < 3 } {
|
|
set RUN_IMPL 0
|
|
}
|
|
|
|
set ENDIAN @ENDIAN@
|
|
set TYPE @TYPE@
|
|
set STRMLEN @STRMLEN@
|
|
set clk "100MHz"
|
|
|
|
if [ expr {$VERSION > 2020.0} ] {
|
|
set CFLAGS "-std=c++11 -Wno-unknown-pragmas -Wno-unused-label -Wall -DNDEBUG -DXILINX_MAJOR=${XILINX_MAJOR} -I${ROOT_DIR}/sources"
|
|
} else {
|
|
set CFLAGS "-std=c++0x -Wno-unknown-pragmas -Wno-unused-label -Wall -DNDEBUG -DXILINX_MAJOR=${XILINX_MAJOR} -I${ROOT_DIR}/sources"
|
|
}
|
|
|
|
|
|
set PROJECT_NAME "${TYPE}_${STRMLEN}_${ENDIAN}_from_bytes_ip"
|
|
open_project -reset "${PROJECT_NAME}"
|
|
set_top ${TYPE}_${STRMLEN}_${ENDIAN}_from_bytes
|
|
add_files "${ROOT_DIR}/sources/CConverter/CConverterFromBytes.cpp" -cflags "${CFLAGS}"
|
|
add_files "${ROOT_DIR}/sources/CConverter/CConverterFromBytes.hpp" -cflags "${CFLAGS}"
|
|
add_files "${ROOT_DIR}/sources/top_converters/${TYPE}_${STRMLEN}_${ENDIAN}_from_bytes.cpp" -cflags "${CFLAGS}"
|
|
add_files "${ROOT_DIR}/sources/top_converters/${TYPE}_${STRMLEN}_${ENDIAN}_from_bytes.hpp" -cflags "${CFLAGS}"
|
|
add_files -tb "${ROOT_DIR}/sources/top_converters/${TYPE}_${STRMLEN}_${ENDIAN}_from_bytes_tb.cpp" -cflags "${CFLAGS}"
|
|
|
|
set SOLUTION_NAME "solution_auto"
|
|
if [ expr {$VERSION > 2020.0} ] {
|
|
open_solution ${SOLUTION_NAME} -flow_target vivado
|
|
} else {
|
|
open_solution ${SOLUTION_NAME}
|
|
}
|
|
|
|
set_part {xc7k325t-ffg900-2}
|
|
create_clock -period ${clk} -name default
|
|
set_clock_uncertainty 10%
|
|
|
|
if { [ file exists "directives.tcl" ] } {
|
|
source "directives.tcl"
|
|
}
|
|
|
|
# set_directive_interface -mode @ITF_BLK@ ${TYPE}_${STRMLEN}_${ENDIAN}_from_bytes
|
|
# set_directive_interface -mode @ITF_IN@ ${TYPE}_${STRMLEN}_${ENDIAN}_from_bytes strm_in
|
|
# set_directive_interface -mode @ITF_OUT@ ${TYPE}_${STRMLEN}_${ENDIAN}_from_bytes strm_out
|
|
|
|
csim_design -clean -O -argv "${NLINES}"
|
|
csynth_design
|
|
cosim_design -O -argv "${NLINES}"
|
|
|
|
config_export \
|
|
-rtl verilog \
|
|
-format ip_catalog \
|
|
-description "Convert ${STRMLEN} ${TYPE} from bytes ${ENDIAN} at ${clk}" \
|
|
-vendor "DrasLorus" \
|
|
-display_name "${STRMLEN} ${TYPE} bus from ${ENDIAN} bytes converter ${clk}" \
|
|
-version "0.1.00${XILINX_MAJOR}" \
|
|
-ipname "bytes${ENDIAN}2${TYPE}_${STRMLEN}_${clk}" \
|
|
-vivado_optimization_level 2 \
|
|
-vivado_phys_opt route
|
|
|
|
if { $EXPORT_IP } {
|
|
if [ expr {! [ file isdirectory "${ROOT_DIR}/ip" ] } ] {
|
|
if { [ file exists "${ROOT_DIR}/ip" ] } {
|
|
file remove "${ROOT_DIR}/ip"
|
|
}
|
|
file mkdir "${ROOT_DIR}/ip"
|
|
}
|
|
|
|
if [ expr {$VERSION > 2020.0} ] {
|
|
export_design -output "${ROOT_DIR}/ip/bytes${ENDIAN}2${TYPE}_${STRMLEN}_${clk}_${XILINX_MAJOR}.zip"
|
|
} else {
|
|
export_design
|
|
set IP_FILE [glob -directory "${PROJECT_NAME}/${SOLUTION_NAME}/impl/ip" -- "*.zip"]
|
|
file copy -force -- "${IP_FILE}" "${ROOT_DIR}/ip/bytes${ENDIAN}2${TYPE}_${STRMLEN}_${clk}_${XILINX_MAJOR}.zip"
|
|
}
|
|
}
|
|
|
|
if { $RUN_IMPL } {
|
|
export_design -flow impl
|
|
}
|
|
|
|
close_solution
|
|
|
|
|
|
close_project
|
|
exit 0
|