From e83310ab23c017ad1127a3d6e369317e807a0a73 Mon Sep 17 00:00:00 2001 From: anonymous Date: Mon, 16 May 2022 19:08:16 +0200 Subject: [PATCH] Fixes for top project inclusion and cleaning - CMakeLists cleansed and sanitized (better inclusion as subproject), - TCL script cleansed, - Formating otherwise. --- CMakeLists.txt | 80 +++++++++++-------- ...ript_type_strmlen_endian_from_bytes.tcl.in | 32 ++++---- ...script_type_strmlen_endian_to_bytes.tcl.in | 32 ++++---- sources/CConverter/CConverterFromBytes.cpp | 26 +++--- sources/CConverter/CConverterToBytes.cpp | 26 +++--- sources/CConverter/CConverterToBytes.hpp | 24 +++--- 6 files changed, 115 insertions(+), 105 deletions(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index b5cf7fc..c89cae3 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -154,25 +154,27 @@ target_include_directories (hls_uart_converters SYSTEM PUBLIC ${AP_INCLUDE_DIR}) set (CFGIN_TO_TOP_CPP "sources/top_converters/type_strmlen_endian_to_bytes.cpp.in") set (CFGOUT_TO_TOP_CPP - "${CMAKE_SOURCE_DIR}/sources/top_converters/${TYPE}_${STRMLEN}_${ENDIAN}_to_bytes.cpp" + "${CMAKE_CURRENT_SOURCE_DIR}/sources/top_converters/${TYPE}_${STRMLEN}_${ENDIAN}_to_bytes.cpp" ) configure_file (${CFGIN_TO_TOP_CPP} ${CFGOUT_TO_TOP_CPP} @ONLY) set (CFGIN_TO_TOP_HPP "sources/top_converters/type_strmlen_endian_to_bytes.hpp.in") set (CFGOUT_TO_TOP_HPP - "${CMAKE_SOURCE_DIR}/sources/top_converters/${TYPE}_${STRMLEN}_${ENDIAN}_to_bytes.hpp" + "${CMAKE_CURRENT_SOURCE_DIR}/sources/top_converters/${TYPE}_${STRMLEN}_${ENDIAN}_to_bytes.hpp" ) configure_file (${CFGIN_TO_TOP_HPP} ${CFGOUT_TO_TOP_HPP} @ONLY) set (CFGIN_TO_TB_CPP "sources/top_converters/type_strmlen_endian_to_bytes_tb.cpp.in") -set (CFGOUT_TO_TB_CPP - "${CMAKE_SOURCE_DIR}/sources/top_converters/${TYPE}_${STRMLEN}_${ENDIAN}_to_bytes_tb.cpp" +set ( + CFGOUT_TO_TB_CPP + "${CMAKE_CURRENT_SOURCE_DIR}/sources/top_converters/${TYPE}_${STRMLEN}_${ENDIAN}_to_bytes_tb.cpp" ) configure_file (${CFGIN_TO_TB_CPP} ${CFGOUT_TO_TB_CPP} @ONLY) set (CFGIN_TO_TCL "hls_files/templates/script_type_strmlen_endian_to_bytes.tcl.in") -set (CFGOUT_TO_TCL - "${CMAKE_SOURCE_DIR}/hls_files/generated/script_${TYPE}_${STRMLEN}_${ENDIAN}_to_bytes.tcl" +set ( + CFGOUT_TO_TCL + "${CMAKE_CURRENT_SOURCE_DIR}/hls_files/generated/script_${TYPE}_${STRMLEN}_${ENDIAN}_to_bytes.tcl" ) configure_file (${CFGIN_TO_TCL} ${CFGOUT_TO_TCL} @ONLY) @@ -186,26 +188,30 @@ target_link_libraries (hls_uart_${TYPE}_${STRMLEN}_${ENDIAN}_to_bytes_tb hls_uar # ################################################################################################## set (CFGIN_FROM_TOP_CPP "sources/top_converters/type_strmlen_endian_from_bytes.cpp.in") -set (CFGOUT_FROM_TOP_CPP - "${CMAKE_SOURCE_DIR}/sources/top_converters/${TYPE}_${STRMLEN}_${ENDIAN}_from_bytes.cpp" +set ( + CFGOUT_FROM_TOP_CPP + "${CMAKE_CURRENT_SOURCE_DIR}/sources/top_converters/${TYPE}_${STRMLEN}_${ENDIAN}_from_bytes.cpp" ) configure_file (${CFGIN_FROM_TOP_CPP} ${CFGOUT_FROM_TOP_CPP} @ONLY) set (CFGIN_FROM_TOP_HPP "sources/top_converters/type_strmlen_endian_from_bytes.hpp.in") -set (CFGOUT_FROM_TOP_HPP - "${CMAKE_SOURCE_DIR}/sources/top_converters/${TYPE}_${STRMLEN}_${ENDIAN}_from_bytes.hpp" +set ( + CFGOUT_FROM_TOP_HPP + "${CMAKE_CURRENT_SOURCE_DIR}/sources/top_converters/${TYPE}_${STRMLEN}_${ENDIAN}_from_bytes.hpp" ) configure_file (${CFGIN_FROM_TOP_HPP} ${CFGOUT_FROM_TOP_HPP} @ONLY) set (CFGIN_FROM_TB_CPP "sources/top_converters/type_strmlen_endian_from_bytes_tb.cpp.in") -set (CFGOUT_FROM_TB_CPP - "${CMAKE_SOURCE_DIR}/sources/top_converters/${TYPE}_${STRMLEN}_${ENDIAN}_from_bytes_tb.cpp" +set ( + CFGOUT_FROM_TB_CPP + "${CMAKE_CURRENT_SOURCE_DIR}/sources/top_converters/${TYPE}_${STRMLEN}_${ENDIAN}_from_bytes_tb.cpp" ) configure_file (${CFGIN_FROM_TB_CPP} ${CFGOUT_FROM_TB_CPP} @ONLY) set (CFGIN_FROM_TCL "hls_files/templates/script_type_strmlen_endian_from_bytes.tcl.in") -set (CFGOUT_FROM_TCL - "${CMAKE_SOURCE_DIR}/hls_files/generated/script_${TYPE}_${STRMLEN}_${ENDIAN}_from_bytes.tcl" +set ( + CFGOUT_FROM_TCL + "${CMAKE_CURRENT_SOURCE_DIR}/hls_files/generated/script_${TYPE}_${STRMLEN}_${ENDIAN}_from_bytes.tcl" ) configure_file (${CFGIN_FROM_TCL} ${CFGOUT_FROM_TCL} @ONLY) @@ -217,27 +223,29 @@ target_link_libraries (hls_uart_${TYPE}_${STRMLEN}_${ENDIAN}_from_bytes_tb hls_u if (ENABLE_TESTING) include (CTest) + if (CMAKE_VERSION VERSION_GREATER_EQUAL 3.19.0) + cmake_policy (SET CMP0110 NEW) + endif () + # find_file (INPUT_DAT_TB input.dat HINTS data NO_CACHE REQUIRED) if (CMAKE_VERSION VERSION_LESS 3.19.0) set (TEST_NAME_TO - "\"Xilinx C-Simulation Testbench ${CMAKE_PROJECT_NAME} ${TYPE} ${STRMLEN} ${ENDIAN} TO\"" + "\"Xilinx C-Simulation Testbench ${PROJECT_NAME} ${TYPE} ${STRMLEN} ${ENDIAN} TO\"" ) else () - cmake_policy (SET CMP0110 NEW) set (TEST_NAME_TO - "Xilinx C-Simulation Testbench ${CMAKE_PROJECT_NAME} ${TYPE} ${STRMLEN} ${ENDIAN} TO" + "Xilinx C-Simulation Testbench ${PROJECT_NAME} ${TYPE} ${STRMLEN} ${ENDIAN} TO" ) endif () add_test (NAME ${TEST_NAME_TO} COMMAND hls_uart_${TYPE}_${STRMLEN}_${ENDIAN}_to_bytes_tb) if (CMAKE_VERSION VERSION_LESS 3.19.0) set (TEST_NAME_FROM - "\"Xilinx C-Simulation Testbench ${CMAKE_PROJECT_NAME} ${TYPE} ${STRMLEN} ${ENDIAN} FROM\"" + "\"Xilinx C-Simulation Testbench ${PROJECT_NAME} ${TYPE} ${STRMLEN} ${ENDIAN} FROM\"" ) else () - cmake_policy (SET CMP0110 NEW) set (TEST_NAME_FROM - "Xilinx C-Simulation Testbench ${CMAKE_PROJECT_NAME} ${TYPE} ${STRMLEN} ${ENDIAN} FROM" + "Xilinx C-Simulation Testbench ${PROJECT_NAME} ${TYPE} ${STRMLEN} ${ENDIAN} FROM" ) endif () add_test (NAME ${TEST_NAME_FROM} COMMAND hls_uart_${TYPE}_${STRMLEN}_${ENDIAN}_from_bytes_tb) @@ -255,50 +263,56 @@ if (ENABLE_TESTING) "1" CACHE INTERNAL "EXPORT_IP" ) - if (XILINX_IMPL) - set ( - RUN_IMPL - "1" - CACHE INTERNAL "RUN_IMPL" - ) - endif () + else () + unset (EXPORT_IP CACHE) endif () + + if (XILINX_IMPL) + set ( + RUN_IMPL + "1" + CACHE INTERNAL "RUN_IMPL" + ) + else () + unset (RUN_IMPL CACHE) + endif () + add_custom_target ( run_hls_to COMMAND ${XILINX_HLS} ${CFGOUT_TO_TCL} ${XILINX_TESTLINES} ${EXPORT_IP} ${RUN_IMPL} - WORKING_DIRECTORY ${CMAKE_SOURCE_DIR}/hls_files + WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}/hls_files USES_TERMINAL ) add_custom_target ( run_hls_from COMMAND ${XILINX_HLS} ${CFGOUT_FROM_TCL} ${XILINX_TESTLINES} ${EXPORT_IP} ${RUN_IMPL} - WORKING_DIRECTORY ${CMAKE_SOURCE_DIR}/hls_files + WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}/hls_files USES_TERMINAL ) if (CMAKE_VERSION VERSION_LESS 3.19.0) set (TCL_TEST_NAME "\"Xilinx HLS TCL Flow TO\"") else () - cmake_policy (SET CMP0110 NEW) set (TCL_TEST_NAME "Xilinx HLS TCL Flow TO") endif () add_test ( NAME ${TCL_TEST_NAME} COMMAND ${XILINX_HLS} ${CFGOUT_TO_TCL} ${XILINX_TESTLINES} 0 0 - WORKING_DIRECTORY ${CMAKE_SOURCE_DIR}/hls_files + WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}/hls_files ) + set_property (TEST ${TCL_TEST_NAME} DISABLED TRUE) if (CMAKE_VERSION VERSION_LESS 3.19.0) set (TCL_TEST_NAME "\"Xilinx HLS TCL Flow FROM\"") else () - cmake_policy (SET CMP0110 NEW) set (TCL_TEST_NAME "Xilinx HLS TCL Flow FROM") endif () add_test ( NAME ${TCL_TEST_NAME} COMMAND ${XILINX_HLS} ${CFGOUT_FROM_TCL} ${XILINX_TESTLINES} 0 0 - WORKING_DIRECTORY ${CMAKE_SOURCE_DIR}/hls_files + WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}/hls_files ) + set_property (TEST ${TCL_TEST_NAME} DISABLED TRUE) endif () endif () diff --git a/hls_files/templates/script_type_strmlen_endian_from_bytes.tcl.in b/hls_files/templates/script_type_strmlen_endian_from_bytes.tcl.in index 463079f..e73baef 100644 --- a/hls_files/templates/script_type_strmlen_endian_from_bytes.tcl.in +++ b/hls_files/templates/script_type_strmlen_endian_from_bytes.tcl.in @@ -78,9 +78,9 @@ set STRMLEN @STRMLEN@ set clk "100MHz" if [ expr {$VERSION > 2020.0} ] { - set CFLAGS "-std=c++11 -Wno-unknown-pragmas -Wno-unused-label -Wall -DNDEBUG -DXILINX_MAJOR=${XILINX_MAJOR} -isystem ${ROOT_DIR}/hls_max_template/sources/modules -I${ROOT_DIR}/sources -I${ROOT_DIR}/CORDIC_Rotate_APFX/RomGenerators/sources" + set CFLAGS "-std=c++11 -Wno-unknown-pragmas -Wno-unused-label -Wall -DNDEBUG -DXILINX_MAJOR=${XILINX_MAJOR} -I${ROOT_DIR}/sources" } else { - set CFLAGS "-std=c++0x -Wno-unknown-pragmas -Wno-unused-label -Wall -DNDEBUG -DXILINX_MAJOR=${XILINX_MAJOR} -isystem ${ROOT_DIR}/hls_max_template/sources/modules -I${ROOT_DIR}/sources -I${ROOT_DIR}/CORDIC_Rotate_APFX/RomGenerators/sources" + set CFLAGS "-std=c++0x -Wno-unknown-pragmas -Wno-unused-label -Wall -DNDEBUG -DXILINX_MAJOR=${XILINX_MAJOR} -I${ROOT_DIR}/sources" } @@ -114,18 +114,18 @@ csim_design -clean -O -argv "${NLINES}" csynth_design cosim_design -O -argv "${NLINES}" -if { $EXPORT_IP } { - config_export \ - -rtl verilog \ - -format ip_catalog \ - -description "Convert ${STRMLEN} ${TYPE} from bytes ${ENDIAN} at ${clk}" \ - -vendor "DrasLorus" \ - -display_name "${STRMLEN} ${TYPE} bus from ${ENDIAN} bytes converter ${clk}" \ - -version "0.1.00${XILINX_MAJOR}" \ - -ipname "bytes${ENDIAN}2${TYPE}_${STRMLEN}_${clk}" \ - -vivado_optimization_level 2 \ - -vivado_phys_opt route +config_export \ + -rtl verilog \ + -format ip_catalog \ + -description "Convert ${STRMLEN} ${TYPE} from bytes ${ENDIAN} at ${clk}" \ + -vendor "DrasLorus" \ + -display_name "${STRMLEN} ${TYPE} bus from ${ENDIAN} bytes converter ${clk}" \ + -version "0.1.00${XILINX_MAJOR}" \ + -ipname "bytes${ENDIAN}2${TYPE}_${STRMLEN}_${clk}" \ + -vivado_optimization_level 2 \ + -vivado_phys_opt route +if { $EXPORT_IP } { if [ expr {! [ file isdirectory "${ROOT_DIR}/ip" ] } ] { if { [ file exists "${ROOT_DIR}/ip" ] } { file remove "${ROOT_DIR}/ip" @@ -140,10 +140,10 @@ if { $EXPORT_IP } { set IP_FILE [glob -directory "${PROJECT_NAME}/${SOLUTION_NAME}/impl/ip" -- "*.zip"] file copy -force -- "${IP_FILE}" "${ROOT_DIR}/ip/bytes${ENDIAN}2${TYPE}_${STRMLEN}_${clk}_${XILINX_MAJOR}.zip" } +} - if { $RUN_IMPL } { - export_design -flow impl - } +if { $RUN_IMPL } { + export_design -flow impl } close_solution diff --git a/hls_files/templates/script_type_strmlen_endian_to_bytes.tcl.in b/hls_files/templates/script_type_strmlen_endian_to_bytes.tcl.in index c76d5db..87db1e3 100644 --- a/hls_files/templates/script_type_strmlen_endian_to_bytes.tcl.in +++ b/hls_files/templates/script_type_strmlen_endian_to_bytes.tcl.in @@ -78,9 +78,9 @@ set STRMLEN @STRMLEN@ set clk "100MHz" if [ expr {$VERSION > 2020.0} ] { - set CFLAGS "-std=c++11 -Wno-unknown-pragmas -Wno-unused-label -Wall -DNDEBUG -DXILINX_MAJOR=${XILINX_MAJOR} -isystem ${ROOT_DIR}/hls_max_template/sources/modules -I${ROOT_DIR}/sources -I${ROOT_DIR}/CORDIC_Rotate_APFX/RomGenerators/sources" + set CFLAGS "-std=c++11 -Wno-unknown-pragmas -Wno-unused-label -Wall -DNDEBUG -DXILINX_MAJOR=${XILINX_MAJOR} -I${ROOT_DIR}/sources" } else { - set CFLAGS "-std=c++0x -Wno-unknown-pragmas -Wno-unused-label -Wall -DNDEBUG -DXILINX_MAJOR=${XILINX_MAJOR} -isystem ${ROOT_DIR}/hls_max_template/sources/modules -I${ROOT_DIR}/sources -I${ROOT_DIR}/CORDIC_Rotate_APFX/RomGenerators/sources" + set CFLAGS "-std=c++0x -Wno-unknown-pragmas -Wno-unused-label -Wall -DNDEBUG -DXILINX_MAJOR=${XILINX_MAJOR} -I${ROOT_DIR}/sources" } @@ -114,18 +114,18 @@ csim_design -clean -O -argv "${NLINES}" csynth_design cosim_design -O -argv "${NLINES}" -if { $EXPORT_IP } { - config_export \ - -rtl verilog \ - -format ip_catalog \ - -description "Convert ${STRMLEN} ${TYPE} to bytes ${ENDIAN} at ${clk}" \ - -vendor "DrasLorus" \ - -display_name "${STRMLEN} ${TYPE} bus to ${ENDIAN} bytes converter ${clk}" \ - -version "0.1.00${XILINX_MAJOR}" \ - -ipname "${TYPE}2bytes${ENDIAN}_${STRMLEN}_${clk}" \ - -vivado_optimization_level 2 \ - -vivado_phys_opt route +config_export \ + -rtl verilog \ + -format ip_catalog \ + -description "Convert ${STRMLEN} ${TYPE} to bytes ${ENDIAN} at ${clk}" \ + -vendor "DrasLorus" \ + -display_name "${STRMLEN} ${TYPE} bus to ${ENDIAN} bytes converter ${clk}" \ + -version "0.1.00${XILINX_MAJOR}" \ + -ipname "${TYPE}2bytes${ENDIAN}_${STRMLEN}_${clk}" \ + -vivado_optimization_level 2 \ + -vivado_phys_opt route +if { $EXPORT_IP } { if [ expr {! [ file isdirectory "${ROOT_DIR}/ip" ] } ] { if { [ file exists "${ROOT_DIR}/ip" ] } { file remove "${ROOT_DIR}/ip" @@ -140,10 +140,10 @@ if { $EXPORT_IP } { set IP_FILE [glob -directory "${PROJECT_NAME}/${SOLUTION_NAME}/impl/ip" -- "*.zip"] file copy -force -- "${IP_FILE}" "${ROOT_DIR}/ip/${TYPE}2bytes${ENDIAN}_${STRMLEN}_${clk}_${XILINX_MAJOR}.zip" } +} - if { $RUN_IMPL } { - export_design -flow impl - } +if { $RUN_IMPL } { + export_design -flow impl } close_solution diff --git a/sources/CConverter/CConverterFromBytes.cpp b/sources/CConverter/CConverterFromBytes.cpp index bd3a454..fa9fcaa 100644 --- a/sources/CConverter/CConverterFromBytes.cpp +++ b/sources/CConverter/CConverterFromBytes.cpp @@ -1,24 +1,24 @@ /* * Copyright or © or Copr. Université de Bretagne-Sud, Lab-STICC, Bordeaux-INP, IMS * Contributor(s) : Camille Monière (2022) - * + * * camille.moniere@univ-ubs.fr, camille.moniere@ims-bordeaux.fr - * + * * This software is a computer program whose purpose is to simulate and implement C-type * to bytes FPGA IPs. - * + * * This software is governed by the CeCILL-B license under French law and - * abiding by the rules of distribution of free software. You can use, + * abiding by the rules of distribution of free software. You can use, * modify and/ or redistribute the software under the terms of the CeCILL-B * license as circulated by CEA, CNRS and INRIA at the following URL - * "http://www.cecill.info". - * + * "http://www.cecill.info". + * * As a counterpart to the access to the source code and rights to copy, * modify and redistribute granted by the license, users are provided only * with a limited warranty and the software's author, the holder of the * economic rights, and the successive licensors have only limited - * liability. - * + * liability. + * * In this respect, the user's attention is drawn to the risks associated * with loading, using, modifying and/or developing or reproducing the * software by the user in light of its specific status of free software, @@ -26,10 +26,10 @@ * therefore means that it is reserved for developers and experienced * professionals having in-depth computer knowledge. Users are therefore * encouraged to load and test the software's suitability as regards their - * requirements in conditions enabling the security of their systems and/or - * data to be ensured and, more generally, to use and operate it in the - * same conditions as regards security. - * + * requirements in conditions enabling the security of their systems and/or + * data to be ensured and, more generally, to use and operate it in the + * same conditions as regards security. + * * The fact that you are presently reading this means that you have had * knowledge of the CeCILL-B license and that you accept its terms. */ @@ -37,6 +37,4 @@ #ifndef _CONVERTER_FROM_BYTES_HPP_ #define _CONVERTER_FROM_BYTES_HPP_ - - #endif // _CONVERTER_FROM_BYTES_HPP_ diff --git a/sources/CConverter/CConverterToBytes.cpp b/sources/CConverter/CConverterToBytes.cpp index c31faf0..1098170 100644 --- a/sources/CConverter/CConverterToBytes.cpp +++ b/sources/CConverter/CConverterToBytes.cpp @@ -1,24 +1,24 @@ /* * Copyright or © or Copr. Université de Bretagne-Sud, Lab-STICC, Bordeaux-INP, IMS * Contributor(s) : Camille Monière (2022) - * + * * camille.moniere@univ-ubs.fr, camille.moniere@ims-bordeaux.fr - * + * * This software is a computer program whose purpose is to simulate and implement C-type * to bytes FPGA IPs. - * + * * This software is governed by the CeCILL-B license under French law and - * abiding by the rules of distribution of free software. You can use, + * abiding by the rules of distribution of free software. You can use, * modify and/ or redistribute the software under the terms of the CeCILL-B * license as circulated by CEA, CNRS and INRIA at the following URL - * "http://www.cecill.info". - * + * "http://www.cecill.info". + * * As a counterpart to the access to the source code and rights to copy, * modify and redistribute granted by the license, users are provided only * with a limited warranty and the software's author, the holder of the * economic rights, and the successive licensors have only limited - * liability. - * + * liability. + * * In this respect, the user's attention is drawn to the risks associated * with loading, using, modifying and/or developing or reproducing the * software by the user in light of its specific status of free software, @@ -26,10 +26,10 @@ * therefore means that it is reserved for developers and experienced * professionals having in-depth computer knowledge. Users are therefore * encouraged to load and test the software's suitability as regards their - * requirements in conditions enabling the security of their systems and/or - * data to be ensured and, more generally, to use and operate it in the - * same conditions as regards security. - * + * requirements in conditions enabling the security of their systems and/or + * data to be ensured and, more generally, to use and operate it in the + * same conditions as regards security. + * * The fact that you are presently reading this means that you have had * knowledge of the CeCILL-B license and that you accept its terms. */ @@ -37,6 +37,4 @@ #ifndef _CONVERTER_TO_BYTES_HPP_ #define _CONVERTER_TO_BYTES_HPP_ - - #endif // _CONVERTER_TO_BYTES_HPP_ diff --git a/sources/CConverter/CConverterToBytes.hpp b/sources/CConverter/CConverterToBytes.hpp index 7d8cee4..19b5f76 100644 --- a/sources/CConverter/CConverterToBytes.hpp +++ b/sources/CConverter/CConverterToBytes.hpp @@ -1,24 +1,24 @@ /* * Copyright or © or Copr. Université de Bretagne-Sud, Lab-STICC, Bordeaux-INP, IMS * Contributor(s) : Camille Monière (2022) - * + * * camille.moniere@univ-ubs.fr, camille.moniere@ims-bordeaux.fr - * + * * This software is a computer program whose purpose is to simulate and implement C-type * to bytes FPGA IPs. - * + * * This software is governed by the CeCILL-B license under French law and - * abiding by the rules of distribution of free software. You can use, + * abiding by the rules of distribution of free software. You can use, * modify and/ or redistribute the software under the terms of the CeCILL-B * license as circulated by CEA, CNRS and INRIA at the following URL - * "http://www.cecill.info". - * + * "http://www.cecill.info". + * * As a counterpart to the access to the source code and rights to copy, * modify and redistribute granted by the license, users are provided only * with a limited warranty and the software's author, the holder of the * economic rights, and the successive licensors have only limited - * liability. - * + * liability. + * * In this respect, the user's attention is drawn to the risks associated * with loading, using, modifying and/or developing or reproducing the * software by the user in light of its specific status of free software, @@ -26,10 +26,10 @@ * therefore means that it is reserved for developers and experienced * professionals having in-depth computer knowledge. Users are therefore * encouraged to load and test the software's suitability as regards their - * requirements in conditions enabling the security of their systems and/or - * data to be ensured and, more generally, to use and operate it in the - * same conditions as regards security. - * + * requirements in conditions enabling the security of their systems and/or + * data to be ensured and, more generally, to use and operate it in the + * same conditions as regards security. + * * The fact that you are presently reading this means that you have had * knowledge of the CeCILL-B license and that you accept its terms. */