From 0dd5ec3785f61f74cfc1c1625234804b846487f4 Mon Sep 17 00:00:00 2001 From: DrasLorus Date: Thu, 12 May 2022 14:06:19 +0200 Subject: [PATCH] Initial commit (no README yet) --- .clang-format | 165 ++++++ .gitignore | 22 + CMakeLists.txt | 304 +++++++++++ LICENSE | 515 ++++++++++++++++++ cmake_format_conf.py | 240 ++++++++ hls_files/generated/.empty | 1 + ...ript_type_strmlen_endian_from_bytes.tcl.in | 153 ++++++ ...script_type_strmlen_endian_to_bytes.tcl.in | 153 ++++++ sources/CConverter/CConverterFromBytes.cpp | 42 ++ sources/CConverter/CConverterFromBytes.hpp | 95 ++++ sources/CConverter/CConverterToBytes.cpp | 42 ++ sources/CConverter/CConverterToBytes.hpp | 93 ++++ .../type_strmlen_endian_from_bytes.cpp.in | 41 ++ .../type_strmlen_endian_from_bytes.hpp.in | 49 ++ .../type_strmlen_endian_from_bytes_tb.cpp.in | 142 +++++ .../type_strmlen_endian_to_bytes.cpp.in | 41 ++ .../type_strmlen_endian_to_bytes.hpp.in | 49 ++ .../type_strmlen_endian_to_bytes_tb.cpp.in | 130 +++++ 18 files changed, 2277 insertions(+) create mode 100644 .clang-format create mode 100644 .gitignore create mode 100644 CMakeLists.txt create mode 100644 LICENSE create mode 100644 cmake_format_conf.py create mode 100644 hls_files/generated/.empty create mode 100644 hls_files/templates/script_type_strmlen_endian_from_bytes.tcl.in create mode 100644 hls_files/templates/script_type_strmlen_endian_to_bytes.tcl.in create mode 100644 sources/CConverter/CConverterFromBytes.cpp create mode 100644 sources/CConverter/CConverterFromBytes.hpp create mode 100644 sources/CConverter/CConverterToBytes.cpp create mode 100644 sources/CConverter/CConverterToBytes.hpp create mode 100644 sources/top_converters/type_strmlen_endian_from_bytes.cpp.in create mode 100644 sources/top_converters/type_strmlen_endian_from_bytes.hpp.in create mode 100644 sources/top_converters/type_strmlen_endian_from_bytes_tb.cpp.in create mode 100644 sources/top_converters/type_strmlen_endian_to_bytes.cpp.in create mode 100644 sources/top_converters/type_strmlen_endian_to_bytes.hpp.in create mode 100644 sources/top_converters/type_strmlen_endian_to_bytes_tb.cpp.in diff --git a/.clang-format b/.clang-format new file mode 100644 index 0000000..dbdada7 --- /dev/null +++ b/.clang-format @@ -0,0 +1,165 @@ +--- +Language: Cpp +AccessModifierOffset: -4 +AlignAfterOpenBracket: Align +AlignConsecutiveMacros: Consecutive +AlignConsecutiveAssignments: Consecutive +AlignConsecutiveBitFields: Consecutive +AlignConsecutiveDeclarations: Consecutive +AlignEscapedNewlines: Right +AlignOperands: AlignAfterOperator +AlignTrailingComments: true +AllowAllArgumentsOnNextLine: true +AllowAllConstructorInitializersOnNextLine: false +AllowAllParametersOfDeclarationOnNextLine: true +AllowShortEnumsOnASingleLine: true +AllowShortBlocksOnASingleLine: Never +AllowShortCaseLabelsOnASingleLine: false +AllowShortFunctionsOnASingleLine: All +AllowShortLambdasOnASingleLine: All +AllowShortIfStatementsOnASingleLine: Never +AllowShortLoopsOnASingleLine: false +AlwaysBreakAfterDefinitionReturnType: None +AlwaysBreakAfterReturnType: None +AlwaysBreakBeforeMultilineStrings: false +AlwaysBreakTemplateDeclarations: MultiLine +AttributeMacros: + - __capability +BinPackArguments: true +BinPackParameters: true +BraceWrapping: + AfterCaseLabel: false + AfterClass: false + AfterControlStatement: Never + AfterEnum: false + AfterFunction: false + AfterNamespace: false + AfterObjCDeclaration: false + AfterStruct: false + AfterUnion: false + AfterExternBlock: false + BeforeCatch: false + BeforeElse: false + BeforeLambdaBody: false + BeforeWhile: false + IndentBraces: false + SplitEmptyFunction: true + SplitEmptyRecord: true + SplitEmptyNamespace: true +BreakBeforeBinaryOperators: true +BreakBeforeConceptDeclarations: true +BreakBeforeBraces: Attach +BreakBeforeInheritanceComma: false +BreakInheritanceList: BeforeColon +BreakBeforeTernaryOperators: true +BreakConstructorInitializersBeforeComma: false +BreakConstructorInitializers: BeforeColon +BreakAfterJavaFieldAnnotations: true +BreakStringLiterals: true +ColumnLimit: 0 +CommentPragmas: '^ IWYU pragma:' +CompactNamespaces: false +ConstructorInitializerAllOnOneLineOrOnePerLine: true +ConstructorInitializerIndentWidth: 4 +ContinuationIndentWidth: 4 +Cpp11BracedListStyle: true +DeriveLineEnding: true +DerivePointerAlignment: false +DisableFormat: false +EmptyLineBeforeAccessModifier: LogicalBlock +ExperimentalAutoDetectBinPacking: false +FixNamespaceComments: true +ForEachMacros: + - foreach + - Q_FOREACH + - BOOST_FOREACH +StatementAttributeLikeMacros: + - Q_EMIT +IncludeBlocks: Preserve +IncludeCategories: + - Regex: '^"(llvm|llvm-c|clang|clang-c)/' + Priority: 2 + SortPriority: 0 + CaseSensitive: false + - Regex: '^(<|"(gtest|gmock|isl|json)/)' + Priority: 3 + SortPriority: 0 + CaseSensitive: false + - Regex: '.*' + Priority: 1 + SortPriority: 0 + CaseSensitive: false +IncludeIsMainRegex: '(Test)?$' +IncludeIsMainSourceRegex: '' +IndentCaseLabels: true +IndentCaseBlocks: false +IndentGotoLabels: true +IndentPPDirectives: None +IndentExternBlock: AfterExternBlock +IndentRequires: false +IndentWidth: 4 +IndentWrappedFunctionNames: false +InsertTrailingCommas: None +JavaScriptQuotes: Leave +JavaScriptWrapImports: true +KeepEmptyLinesAtTheStartOfBlocks: true +MacroBlockBegin: '' +MacroBlockEnd: '' +MaxEmptyLinesToKeep: 1 +NamespaceIndentation: None +ObjCBinPackProtocolList: Auto +ObjCBlockIndentWidth: 2 +ObjCBreakBeforeNestedBlockParam: true +ObjCSpaceAfterProperty: false +ObjCSpaceBeforeProtocolList: true +PenaltyBreakAssignment: 2 +PenaltyBreakBeforeFirstCallParameter: 19 +PenaltyBreakComment: 300 +PenaltyBreakFirstLessLess: 120 +PenaltyBreakString: 1000 +PenaltyBreakTemplateDeclaration: 10 +PenaltyExcessCharacter: 1000000 +PenaltyReturnTypeOnItsOwnLine: 60 +PenaltyIndentedWhitespace: 0 +PointerAlignment: Middle +ReflowComments: true +SortIncludes: true +SortJavaStaticImport: Before +SortUsingDeclarations: true +SpaceAfterCStyleCast: true +SpaceAfterLogicalNot: false +SpaceAfterTemplateKeyword: true +SpaceBeforeAssignmentOperators: true +SpaceBeforeCaseColon: false +SpaceBeforeCpp11BracedList: true +SpaceBeforeCtorInitializerColon: true +SpaceBeforeInheritanceColon: true +SpaceBeforeParens: ControlStatements +SpaceAroundPointerQualifiers: Default +SpaceBeforeRangeBasedForLoopColon: true +SpaceInEmptyBlock: false +SpaceInEmptyParentheses: false +SpacesBeforeTrailingComments: 1 +SpacesInAngles: false +SpacesInConditionalStatement: false +SpacesInContainerLiterals: true +SpacesInCStyleCastParentheses: false +SpacesInParentheses: false +SpacesInSquareBrackets: false +SpaceBeforeSquareBrackets: false +BitFieldColonSpacing: Both +Standard: c++14 +StatementMacros: + - Q_UNUSED + - QT_REQUIRE_VERSION +TabWidth: 4 +UseCRLF: false +UseTab: Never +WhitespaceSensitiveMacros: + - STRINGIZE + - PP_STRINGIZE + - BOOST_PP_STRINGIZE + - NS_SWIFT_NAME + - CF_SWIFT_NAME +... + diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..e41bc88 --- /dev/null +++ b/.gitignore @@ -0,0 +1,22 @@ +# Binary directories +.cache/ +bin/ +lib/ +build/ +ip/ +*_*_*_to_bytes_ip/ +*_*_*_from_bytes_ip/ + +# Command Database +compile_commands.json + +hls_files/* + +!hls_files/generated +hls_files/generated/* +!hls_files/generated/.empty + +!hls_files/templates +hls_files/templates/*.tcl + +sources/top_converters/*.?pp diff --git a/CMakeLists.txt b/CMakeLists.txt new file mode 100644 index 0000000..b5cf7fc --- /dev/null +++ b/CMakeLists.txt @@ -0,0 +1,304 @@ +# +# Copyright or © or Copr. Université de Bretagne-Sud, Lab-STICC, Bordeaux-INP, IMS Contributor(s) : +# Camille Monière (2022) +# +# camille.moniere@univ-ubs.fr, camille.moniere@ims-bordeaux.fr +# +# This software is a computer program whose purpose is to simulate and implement C-type to bytes +# FPGA IPs. +# +# This software is governed by the CeCILL-B license under French law and abiding by the rules of +# distribution of free software. You can use, modify and/ or redistribute the software under the +# terms of the CeCILL-B license as circulated by CEA, CNRS and INRIA at the following URL +# "http://www.cecill.info". +# +# As a counterpart to the access to the source code and rights to copy, modify and redistribute +# granted by the license, users are provided only with a limited warranty and the software's +# author, the holder of the economic rights, and the successive licensors have only limited +# liability. +# +# In this respect, the user's attention is drawn to the risks associated with loading, using, +# modifying and/or developing or reproducing the software by the user in light of its specific +# status of free software, that may mean that it is complicated to manipulate, and that also +# therefore means that it is reserved for developers and experienced professionals having +# in-depth computer knowledge. Users are therefore encouraged to load and test the software's +# suitability as regards their requirements in conditions enabling the security of their systems +# and/or data to be ensured and, more generally, to use and operate it in the same conditions as +# regards security. +# +# The fact that you are presently reading this means that you have had knowledge of the CeCILL-B +# license and that you accept its terms. +# + +cmake_minimum_required (VERSION 3.18.0 FATAL_ERROR) +# setting this is required + +project ( + UartWrapperHLS + LANGUAGES CXX + VERSION 0.1 +) + +set (CMAKE_CXX_STANDARD 11) +set (CMAKE_CXX_STANDARD_REQUIRED ON) +set (CMAKE_CXX_EXTENSIONS OFF) + +set (CMAKE_ARCHIVE_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}/../lib) +set (CMAKE_LIBRARY_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}/../lib) +set (CMAKE_RUNTIME_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}/../bin) + +# ################################################################################################## +# Options +# ################################################################################################## + +option (EXPORT_COMMANDS "export compile commands, for use with clangd for example." ON) + +option (XILINX_COSIM "use TCL Vivado/Vitis HLS script to co-simulate the design." OFF) +if (XILINX_COSIM) + option (XILINX_IP "use TCL Vivado/Vitis HLS script to generate an IP." OFF) + if (XILINX_IP) + option (XILINX_IMPL "use TCL Vivado/Vitis HLS script to run design implementation." OFF) + endif () +endif () + +option (ENABLE_TESTING "use CTest as a test suite." ON) + +option (PEDANTIC "use -Wall and -pedantic." ON) + +# ################################################################################################## +# Parameters +# ################################################################################################## + +set ( + PRM_TYPE + "uint32_t" + CACHE STRING "Type to convert to/from." +) +set (TYPE ${PRM_TYPE}) + +set ( + PRM_STRMLEN + "1" + CACHE STRING "Size of the TYPE stream." +) +set (STRMLEN ${PRM_STRMLEN}) + +set ( + PRM_ENDIAN + "LE" + CACHE STRING "Byte stream endianess." +) +set (ENDIAN ${PRM_ENDIAN}) + +# ################################################################################################## + +if (PEDANTIC) + add_compile_options (-Wall -pedantic) +endif () +add_compile_options (-Wno-unused-label -Wno-unknown-pragmas) + +if (EXPORT_COMMANDS) + set (CMAKE_EXPORT_COMPILE_COMMANDS ON) +endif () + +set ( + XILINX_HOME + /opt/Xilinx + CACHE PATH "path to Xilinx root folder." +) +set ( + XILINX_VER + "2019.1" + CACHE STRING "Xilinx software version to use." +) + +if (XILINX_VER VERSION_GREATER_EQUAL "2020.1") + set ( + AP_INCLUDE_DIR + ${XILINX_HOME}/Vitis_HLS/${XILINX_VER}/include + CACHE INTERNAL "Path to Xilinx includes" FORCE + ) + find_program ( + XILINX_HLS vitis_hls HINTS ${XILINX_HOME}/Vitis_HLS/${XILINX_VER}/bin NO_CACHE REQUIRED + ) +else () + set ( + AP_INCLUDE_DIR + ${XILINX_HOME}/Vivado/${XILINX_VER}/include + CACHE INTERNAL "Path to Xilinx includes" FORCE + ) + find_program ( + XILINX_HLS vivado_hls HINTS ${XILINX_HOME}/Vivado/${XILINX_VER}/bin NO_CACHE REQUIRED + ) +endif () +message (STATUS "AP headers must lie under ${AP_INCLUDE_DIR}") + +if ((NOT EXISTS ${AP_INCLUDE_DIR}/ap_int.h) OR (NOT EXISTS ${AP_INCLUDE_DIR}/ap_fixed.h)) + message (FATAL_ERROR "Arbitrary precision headers not found in ${AP_INCLUDE_DIR}.\n" + "Please provide a suitable path to the headers." + ) +endif () + +# ################################################################################################## + +add_library ( + hls_uart_converters sources/CConverter/CConverterToBytes.cpp + sources/CConverter/CConverterFromBytes.cpp +) +target_include_directories (hls_uart_converters PUBLIC sources) +target_include_directories (hls_uart_converters SYSTEM PUBLIC ${AP_INCLUDE_DIR}) + +# ################################################################################################## +# TO BYTES ###################################################################################### +# ################################################################################################## + +set (CFGIN_TO_TOP_CPP "sources/top_converters/type_strmlen_endian_to_bytes.cpp.in") +set (CFGOUT_TO_TOP_CPP + "${CMAKE_SOURCE_DIR}/sources/top_converters/${TYPE}_${STRMLEN}_${ENDIAN}_to_bytes.cpp" +) +configure_file (${CFGIN_TO_TOP_CPP} ${CFGOUT_TO_TOP_CPP} @ONLY) + +set (CFGIN_TO_TOP_HPP "sources/top_converters/type_strmlen_endian_to_bytes.hpp.in") +set (CFGOUT_TO_TOP_HPP + "${CMAKE_SOURCE_DIR}/sources/top_converters/${TYPE}_${STRMLEN}_${ENDIAN}_to_bytes.hpp" +) +configure_file (${CFGIN_TO_TOP_HPP} ${CFGOUT_TO_TOP_HPP} @ONLY) + +set (CFGIN_TO_TB_CPP "sources/top_converters/type_strmlen_endian_to_bytes_tb.cpp.in") +set (CFGOUT_TO_TB_CPP + "${CMAKE_SOURCE_DIR}/sources/top_converters/${TYPE}_${STRMLEN}_${ENDIAN}_to_bytes_tb.cpp" +) +configure_file (${CFGIN_TO_TB_CPP} ${CFGOUT_TO_TB_CPP} @ONLY) + +set (CFGIN_TO_TCL "hls_files/templates/script_type_strmlen_endian_to_bytes.tcl.in") +set (CFGOUT_TO_TCL + "${CMAKE_SOURCE_DIR}/hls_files/generated/script_${TYPE}_${STRMLEN}_${ENDIAN}_to_bytes.tcl" +) +configure_file (${CFGIN_TO_TCL} ${CFGOUT_TO_TCL} @ONLY) + +add_executable ( + hls_uart_${TYPE}_${STRMLEN}_${ENDIAN}_to_bytes_tb ${CFGOUT_TO_TOP_CPP} ${CFGOUT_TO_TB_CPP} +) +target_link_libraries (hls_uart_${TYPE}_${STRMLEN}_${ENDIAN}_to_bytes_tb hls_uart_converters) + +# ################################################################################################## +# FROM BYTES ###################################################################################### +# ################################################################################################## + +set (CFGIN_FROM_TOP_CPP "sources/top_converters/type_strmlen_endian_from_bytes.cpp.in") +set (CFGOUT_FROM_TOP_CPP + "${CMAKE_SOURCE_DIR}/sources/top_converters/${TYPE}_${STRMLEN}_${ENDIAN}_from_bytes.cpp" +) +configure_file (${CFGIN_FROM_TOP_CPP} ${CFGOUT_FROM_TOP_CPP} @ONLY) + +set (CFGIN_FROM_TOP_HPP "sources/top_converters/type_strmlen_endian_from_bytes.hpp.in") +set (CFGOUT_FROM_TOP_HPP + "${CMAKE_SOURCE_DIR}/sources/top_converters/${TYPE}_${STRMLEN}_${ENDIAN}_from_bytes.hpp" +) +configure_file (${CFGIN_FROM_TOP_HPP} ${CFGOUT_FROM_TOP_HPP} @ONLY) + +set (CFGIN_FROM_TB_CPP "sources/top_converters/type_strmlen_endian_from_bytes_tb.cpp.in") +set (CFGOUT_FROM_TB_CPP + "${CMAKE_SOURCE_DIR}/sources/top_converters/${TYPE}_${STRMLEN}_${ENDIAN}_from_bytes_tb.cpp" +) +configure_file (${CFGIN_FROM_TB_CPP} ${CFGOUT_FROM_TB_CPP} @ONLY) + +set (CFGIN_FROM_TCL "hls_files/templates/script_type_strmlen_endian_from_bytes.tcl.in") +set (CFGOUT_FROM_TCL + "${CMAKE_SOURCE_DIR}/hls_files/generated/script_${TYPE}_${STRMLEN}_${ENDIAN}_from_bytes.tcl" +) +configure_file (${CFGIN_FROM_TCL} ${CFGOUT_FROM_TCL} @ONLY) + +add_executable ( + hls_uart_${TYPE}_${STRMLEN}_${ENDIAN}_from_bytes_tb ${CFGOUT_FROM_TOP_CPP} ${CFGOUT_FROM_TB_CPP} +) +target_link_libraries (hls_uart_${TYPE}_${STRMLEN}_${ENDIAN}_from_bytes_tb hls_uart_converters) + +if (ENABLE_TESTING) + include (CTest) + + # find_file (INPUT_DAT_TB input.dat HINTS data NO_CACHE REQUIRED) + if (CMAKE_VERSION VERSION_LESS 3.19.0) + set (TEST_NAME_TO + "\"Xilinx C-Simulation Testbench ${CMAKE_PROJECT_NAME} ${TYPE} ${STRMLEN} ${ENDIAN} TO\"" + ) + else () + cmake_policy (SET CMP0110 NEW) + set (TEST_NAME_TO + "Xilinx C-Simulation Testbench ${CMAKE_PROJECT_NAME} ${TYPE} ${STRMLEN} ${ENDIAN} TO" + ) + endif () + add_test (NAME ${TEST_NAME_TO} COMMAND hls_uart_${TYPE}_${STRMLEN}_${ENDIAN}_to_bytes_tb) + + if (CMAKE_VERSION VERSION_LESS 3.19.0) + set (TEST_NAME_FROM + "\"Xilinx C-Simulation Testbench ${CMAKE_PROJECT_NAME} ${TYPE} ${STRMLEN} ${ENDIAN} FROM\"" + ) + else () + cmake_policy (SET CMP0110 NEW) + set (TEST_NAME_FROM + "Xilinx C-Simulation Testbench ${CMAKE_PROJECT_NAME} ${TYPE} ${STRMLEN} ${ENDIAN} FROM" + ) + endif () + add_test (NAME ${TEST_NAME_FROM} COMMAND hls_uart_${TYPE}_${STRMLEN}_${ENDIAN}_from_bytes_tb) + + if (XILINX_COSIM) + set ( + XILINX_TESTLINES + "1000" + CACHE STRING "Number of co-simulation passes" + ) + + if (XILINX_IP) + set ( + EXPORT_IP + "1" + CACHE INTERNAL "EXPORT_IP" + ) + if (XILINX_IMPL) + set ( + RUN_IMPL + "1" + CACHE INTERNAL "RUN_IMPL" + ) + endif () + endif () + add_custom_target ( + run_hls_to + COMMAND ${XILINX_HLS} ${CFGOUT_TO_TCL} ${XILINX_TESTLINES} ${EXPORT_IP} ${RUN_IMPL} + WORKING_DIRECTORY ${CMAKE_SOURCE_DIR}/hls_files + USES_TERMINAL + ) + + add_custom_target ( + run_hls_from + COMMAND ${XILINX_HLS} ${CFGOUT_FROM_TCL} ${XILINX_TESTLINES} ${EXPORT_IP} ${RUN_IMPL} + WORKING_DIRECTORY ${CMAKE_SOURCE_DIR}/hls_files + USES_TERMINAL + ) + + if (CMAKE_VERSION VERSION_LESS 3.19.0) + set (TCL_TEST_NAME "\"Xilinx HLS TCL Flow TO\"") + else () + cmake_policy (SET CMP0110 NEW) + set (TCL_TEST_NAME "Xilinx HLS TCL Flow TO") + endif () + add_test ( + NAME ${TCL_TEST_NAME} + COMMAND ${XILINX_HLS} ${CFGOUT_TO_TCL} ${XILINX_TESTLINES} 0 0 + WORKING_DIRECTORY ${CMAKE_SOURCE_DIR}/hls_files + ) + + if (CMAKE_VERSION VERSION_LESS 3.19.0) + set (TCL_TEST_NAME "\"Xilinx HLS TCL Flow FROM\"") + else () + cmake_policy (SET CMP0110 NEW) + set (TCL_TEST_NAME "Xilinx HLS TCL Flow FROM") + endif () + add_test ( + NAME ${TCL_TEST_NAME} + COMMAND ${XILINX_HLS} ${CFGOUT_FROM_TCL} ${XILINX_TESTLINES} 0 0 + WORKING_DIRECTORY ${CMAKE_SOURCE_DIR}/hls_files + ) + endif () +endif () diff --git a/LICENSE b/LICENSE new file mode 100644 index 0000000..da41897 --- /dev/null +++ b/LICENSE @@ -0,0 +1,515 @@ + +CeCILL-B FREE SOFTWARE LICENSE AGREEMENT + + + Notice + +This Agreement is a Free Software license agreement that is the result +of discussions between its authors in order to ensure compliance with +the two main principles guiding its drafting: + + * firstly, compliance with the principles governing the distribution + of Free Software: access to source code, broad rights granted to + users, + * secondly, the election of a governing law, French law, with which + it is conformant, both as regards the law of torts and + intellectual property law, and the protection that it offers to + both authors and holders of the economic rights over software. + +The authors of the CeCILL-B (for Ce[a] C[nrs] I[nria] L[ogiciel] L[ibre]) +license are: + +Commissariat à l'Energie Atomique - CEA, a public scientific, technical +and industrial research establishment, having its principal place of +business at 25 rue Leblanc, immeuble Le Ponant D, 75015 Paris, France. + +Centre National de la Recherche Scientifique - CNRS, a public scientific +and technological establishment, having its principal place of business +at 3 rue Michel-Ange, 75794 Paris cedex 16, France. + +Institut National de Recherche en Informatique et en Automatique - +INRIA, a public scientific and technological establishment, having its +principal place of business at Domaine de Voluceau, Rocquencourt, BP +105, 78153 Le Chesnay cedex, France. + + + Preamble + +This Agreement is an open source software license intended to give users +significant freedom to modify and redistribute the software licensed +hereunder. + +The exercising of this freedom is conditional upon a strong obligation +of giving credits for everybody that distributes a software +incorporating a software ruled by the current license so as all +contributions to be properly identified and acknowledged. + +In consideration of access to the source code and the rights to copy, +modify and redistribute granted by the license, users are provided only +with a limited warranty and the software's author, the holder of the +economic rights, and the successive licensors only have limited liability. + +In this respect, the risks associated with loading, using, modifying +and/or developing or reproducing the software by the user are brought to +the user's attention, given its Free Software status, which may make it +complicated to use, with the result that its use is reserved for +developers and experienced professionals having in-depth computer +knowledge. Users are therefore encouraged to load and test the +suitability of the software as regards their requirements in conditions +enabling the security of their systems and/or data to be ensured and, +more generally, to use and operate it in the same conditions of +security. This Agreement may be freely reproduced and published, +provided it is not altered, and that no provisions are either added or +removed herefrom. + +This Agreement may apply to any or all software for which the holder of +the economic rights decides to submit the use thereof to its provisions. + + + Article 1 - DEFINITIONS + +For the purpose of this Agreement, when the following expressions +commence with a capital letter, they shall have the following meaning: + +Agreement: means this license agreement, and its possible subsequent +versions and annexes. + +Software: means the software in its Object Code and/or Source Code form +and, where applicable, its documentation, "as is" when the Licensee +accepts the Agreement. + +Initial Software: means the Software in its Source Code and possibly its +Object Code form and, where applicable, its documentation, "as is" when +it is first distributed under the terms and conditions of the Agreement. + +Modified Software: means the Software modified by at least one +Contribution. + +Source Code: means all the Software's instructions and program lines to +which access is required so as to modify the Software. + +Object Code: means the binary files originating from the compilation of +the Source Code. + +Holder: means the holder(s) of the economic rights over the Initial +Software. + +Licensee: means the Software user(s) having accepted the Agreement. + +Contributor: means a Licensee having made at least one Contribution. + +Licensor: means the Holder, or any other individual or legal entity, who +distributes the Software under the Agreement. + +Contribution: means any or all modifications, corrections, translations, +adaptations and/or new functions integrated into the Software by any or +all Contributors, as well as any or all Internal Modules. + +Module: means a set of sources files including their documentation that +enables supplementary functions or services in addition to those offered +by the Software. + +External Module: means any or all Modules, not derived from the +Software, so that this Module and the Software run in separate address +spaces, with one calling the other when they are run. + +Internal Module: means any or all Module, connected to the Software so +that they both execute in the same address space. + +Parties: mean both the Licensee and the Licensor. + +These expressions may be used both in singular and plural form. + + + Article 2 - PURPOSE + +The purpose of the Agreement is the grant by the Licensor to the +Licensee of a non-exclusive, transferable and worldwide license for the +Software as set forth in Article 5 hereinafter for the whole term of the +protection granted by the rights over said Software. + + + Article 3 - ACCEPTANCE + +3.1 The Licensee shall be deemed as having accepted the terms and +conditions of this Agreement upon the occurrence of the first of the +following events: + + * (i) loading the Software by any or all means, notably, by + downloading from a remote server, or by loading from a physical + medium; + * (ii) the first time the Licensee exercises any of the rights + granted hereunder. + +3.2 One copy of the Agreement, containing a notice relating to the +characteristics of the Software, to the limited warranty, and to the +fact that its use is restricted to experienced users has been provided +to the Licensee prior to its acceptance as set forth in Article 3.1 +hereinabove, and the Licensee hereby acknowledges that it has read and +understood it. + + + Article 4 - EFFECTIVE DATE AND TERM + + + 4.1 EFFECTIVE DATE + +The Agreement shall become effective on the date when it is accepted by +the Licensee as set forth in Article 3.1. + + + 4.2 TERM + +The Agreement shall remain in force for the entire legal term of +protection of the economic rights over the Software. + + + Article 5 - SCOPE OF RIGHTS GRANTED + +The Licensor hereby grants to the Licensee, who accepts, the following +rights over the Software for any or all use, and for the term of the +Agreement, on the basis of the terms and conditions set forth hereinafter. + +Besides, if the Licensor owns or comes to own one or more patents +protecting all or part of the functions of the Software or of its +components, the Licensor undertakes not to enforce the rights granted by +these patents against successive Licensees using, exploiting or +modifying the Software. If these patents are transferred, the Licensor +undertakes to have the transferees subscribe to the obligations set +forth in this paragraph. + + + 5.1 RIGHT OF USE + +The Licensee is authorized to use the Software, without any limitation +as to its fields of application, with it being hereinafter specified +that this comprises: + + 1. permanent or temporary reproduction of all or part of the Software + by any or all means and in any or all form. + + 2. loading, displaying, running, or storing the Software on any or + all medium. + + 3. entitlement to observe, study or test its operation so as to + determine the ideas and principles behind any or all constituent + elements of said Software. This shall apply when the Licensee + carries out any or all loading, displaying, running, transmission + or storage operation as regards the Software, that it is entitled + to carry out hereunder. + + + 5.2 ENTITLEMENT TO MAKE CONTRIBUTIONS + +The right to make Contributions includes the right to translate, adapt, +arrange, or make any or all modifications to the Software, and the right +to reproduce the resulting software. + +The Licensee is authorized to make any or all Contributions to the +Software provided that it includes an explicit notice that it is the +author of said Contribution and indicates the date of the creation thereof. + + + 5.3 RIGHT OF DISTRIBUTION + +In particular, the right of distribution includes the right to publish, +transmit and communicate the Software to the general public on any or +all medium, and by any or all means, and the right to market, either in +consideration of a fee, or free of charge, one or more copies of the +Software by any means. + +The Licensee is further authorized to distribute copies of the modified +or unmodified Software to third parties according to the terms and +conditions set forth hereinafter. + + + 5.3.1 DISTRIBUTION OF SOFTWARE WITHOUT MODIFICATION + +The Licensee is authorized to distribute true copies of the Software in +Source Code or Object Code form, provided that said distribution +complies with all the provisions of the Agreement and is accompanied by: + + 1. a copy of the Agreement, + + 2. a notice relating to the limitation of both the Licensor's + warranty and liability as set forth in Articles 8 and 9, + +and that, in the event that only the Object Code of the Software is +redistributed, the Licensee allows effective access to the full Source +Code of the Software at a minimum during the entire period of its +distribution of the Software, it being understood that the additional +cost of acquiring the Source Code shall not exceed the cost of +transferring the data. + + + 5.3.2 DISTRIBUTION OF MODIFIED SOFTWARE + +If the Licensee makes any Contribution to the Software, the resulting +Modified Software may be distributed under a license agreement other +than this Agreement subject to compliance with the provisions of Article +5.3.4. + + + 5.3.3 DISTRIBUTION OF EXTERNAL MODULES + +When the Licensee has developed an External Module, the terms and +conditions of this Agreement do not apply to said External Module, that +may be distributed under a separate license agreement. + + + 5.3.4 CREDITS + +Any Licensee who may distribute a Modified Software hereby expressly +agrees to: + + 1. indicate in the related documentation that it is based on the + Software licensed hereunder, and reproduce the intellectual + property notice for the Software, + + 2. ensure that written indications of the Software intended use, + intellectual property notice and license hereunder are included in + easily accessible format from the Modified Software interface, + + 3. mention, on a freely accessible website describing the Modified + Software, at least throughout the distribution term thereof, that + it is based on the Software licensed hereunder, and reproduce the + Software intellectual property notice, + + 4. where it is distributed to a third party that may distribute a + Modified Software without having to make its source code + available, make its best efforts to ensure that said third party + agrees to comply with the obligations set forth in this Article . + +If the Software, whether or not modified, is distributed with an +External Module designed for use in connection with the Software, the +Licensee shall submit said External Module to the foregoing obligations. + + + 5.3.5 COMPATIBILITY WITH THE CeCILL AND CeCILL-C LICENSES + +Where a Modified Software contains a Contribution subject to the CeCILL +license, the provisions set forth in Article 5.3.4 shall be optional. + +A Modified Software may be distributed under the CeCILL-C license. In +such a case the provisions set forth in Article 5.3.4 shall be optional. + + + Article 6 - INTELLECTUAL PROPERTY + + + 6.1 OVER THE INITIAL SOFTWARE + +The Holder owns the economic rights over the Initial Software. Any or +all use of the Initial Software is subject to compliance with the terms +and conditions under which the Holder has elected to distribute its work +and no one shall be entitled to modify the terms and conditions for the +distribution of said Initial Software. + +The Holder undertakes that the Initial Software will remain ruled at +least by this Agreement, for the duration set forth in Article 4.2. + + + 6.2 OVER THE CONTRIBUTIONS + +The Licensee who develops a Contribution is the owner of the +intellectual property rights over this Contribution as defined by +applicable law. + + + 6.3 OVER THE EXTERNAL MODULES + +The Licensee who develops an External Module is the owner of the +intellectual property rights over this External Module as defined by +applicable law and is free to choose the type of agreement that shall +govern its distribution. + + + 6.4 JOINT PROVISIONS + +The Licensee expressly undertakes: + + 1. not to remove, or modify, in any manner, the intellectual property + notices attached to the Software; + + 2. to reproduce said notices, in an identical manner, in the copies + of the Software modified or not. + +The Licensee undertakes not to directly or indirectly infringe the +intellectual property rights of the Holder and/or Contributors on the +Software and to take, where applicable, vis-à-vis its staff, any and all +measures required to ensure respect of said intellectual property rights +of the Holder and/or Contributors. + + + Article 7 - RELATED SERVICES + +7.1 Under no circumstances shall the Agreement oblige the Licensor to +provide technical assistance or maintenance services for the Software. + +However, the Licensor is entitled to offer this type of services. The +terms and conditions of such technical assistance, and/or such +maintenance, shall be set forth in a separate instrument. Only the +Licensor offering said maintenance and/or technical assistance services +shall incur liability therefor. + +7.2 Similarly, any Licensor is entitled to offer to its licensees, under +its sole responsibility, a warranty, that shall only be binding upon +itself, for the redistribution of the Software and/or the Modified +Software, under terms and conditions that it is free to decide. Said +warranty, and the financial terms and conditions of its application, +shall be subject of a separate instrument executed between the Licensor +and the Licensee. + + + Article 8 - LIABILITY + +8.1 Subject to the provisions of Article 8.2, the Licensee shall be +entitled to claim compensation for any direct loss it may have suffered +from the Software as a result of a fault on the part of the relevant +Licensor, subject to providing evidence thereof. + +8.2 The Licensor's liability is limited to the commitments made under +this Agreement and shall not be incurred as a result of in particular: +(i) loss due the Licensee's total or partial failure to fulfill its +obligations, (ii) direct or consequential loss that is suffered by the +Licensee due to the use or performance of the Software, and (iii) more +generally, any consequential loss. In particular the Parties expressly +agree that any or all pecuniary or business loss (i.e. loss of data, +loss of profits, operating loss, loss of customers or orders, +opportunity cost, any disturbance to business activities) or any or all +legal proceedings instituted against the Licensee by a third party, +shall constitute consequential loss and shall not provide entitlement to +any or all compensation from the Licensor. + + + Article 9 - WARRANTY + +9.1 The Licensee acknowledges that the scientific and technical +state-of-the-art when the Software was distributed did not enable all +possible uses to be tested and verified, nor for the presence of +possible defects to be detected. In this respect, the Licensee's +attention has been drawn to the risks associated with loading, using, +modifying and/or developing and reproducing the Software which are +reserved for experienced users. + +The Licensee shall be responsible for verifying, by any or all means, +the suitability of the product for its requirements, its good working +order, and for ensuring that it shall not cause damage to either persons +or properties. + +9.2 The Licensor hereby represents, in good faith, that it is entitled +to grant all the rights over the Software (including in particular the +rights set forth in Article 5). + +9.3 The Licensee acknowledges that the Software is supplied "as is" by +the Licensor without any other express or tacit warranty, other than +that provided for in Article 9.2 and, in particular, without any warranty +as to its commercial value, its secured, safe, innovative or relevant +nature. + +Specifically, the Licensor does not warrant that the Software is free +from any error, that it will operate without interruption, that it will +be compatible with the Licensee's own equipment and software +configuration, nor that it will meet the Licensee's requirements. + +9.4 The Licensor does not either expressly or tacitly warrant that the +Software does not infringe any third party intellectual property right +relating to a patent, software or any other property right. Therefore, +the Licensor disclaims any and all liability towards the Licensee +arising out of any or all proceedings for infringement that may be +instituted in respect of the use, modification and redistribution of the +Software. Nevertheless, should such proceedings be instituted against +the Licensee, the Licensor shall provide it with technical and legal +assistance for its defense. Such technical and legal assistance shall be +decided on a case-by-case basis between the relevant Licensor and the +Licensee pursuant to a memorandum of understanding. The Licensor +disclaims any and all liability as regards the Licensee's use of the +name of the Software. No warranty is given as regards the existence of +prior rights over the name of the Software or as regards the existence +of a trademark. + + + Article 10 - TERMINATION + +10.1 In the event of a breach by the Licensee of its obligations +hereunder, the Licensor may automatically terminate this Agreement +thirty (30) days after notice has been sent to the Licensee and has +remained ineffective. + +10.2 A Licensee whose Agreement is terminated shall no longer be +authorized to use, modify or distribute the Software. However, any +licenses that it may have granted prior to termination of the Agreement +shall remain valid subject to their having been granted in compliance +with the terms and conditions hereof. + + + Article 11 - MISCELLANEOUS + + + 11.1 EXCUSABLE EVENTS + +Neither Party shall be liable for any or all delay, or failure to +perform the Agreement, that may be attributable to an event of force +majeure, an act of God or an outside cause, such as defective +functioning or interruptions of the electricity or telecommunications +networks, network paralysis following a virus attack, intervention by +government authorities, natural disasters, water damage, earthquakes, +fire, explosions, strikes and labor unrest, war, etc. + +11.2 Any failure by either Party, on one or more occasions, to invoke +one or more of the provisions hereof, shall under no circumstances be +interpreted as being a waiver by the interested Party of its right to +invoke said provision(s) subsequently. + +11.3 The Agreement cancels and replaces any or all previous agreements, +whether written or oral, between the Parties and having the same +purpose, and constitutes the entirety of the agreement between said +Parties concerning said purpose. No supplement or modification to the +terms and conditions hereof shall be effective as between the Parties +unless it is made in writing and signed by their duly authorized +representatives. + +11.4 In the event that one or more of the provisions hereof were to +conflict with a current or future applicable act or legislative text, +said act or legislative text shall prevail, and the Parties shall make +the necessary amendments so as to comply with said act or legislative +text. All other provisions shall remain effective. Similarly, invalidity +of a provision of the Agreement, for any reason whatsoever, shall not +cause the Agreement as a whole to be invalid. + + + 11.5 LANGUAGE + +The Agreement is drafted in both French and English and both versions +are deemed authentic. + + + Article 12 - NEW VERSIONS OF THE AGREEMENT + +12.1 Any person is authorized to duplicate and distribute copies of this +Agreement. + +12.2 So as to ensure coherence, the wording of this Agreement is +protected and may only be modified by the authors of the License, who +reserve the right to periodically publish updates or new versions of the +Agreement, each with a separate number. These subsequent versions may +address new issues encountered by Free Software. + +12.3 Any Software distributed under a given version of the Agreement may +only be subsequently distributed under the same version of the Agreement +or a subsequent version. + + + Article 13 - GOVERNING LAW AND JURISDICTION + +13.1 The Agreement is governed by French law. The Parties agree to +endeavor to seek an amicable solution to any disagreements or disputes +that may arise during the performance of the Agreement. + +13.2 Failing an amicable solution within two (2) months as from their +occurrence, and unless emergency proceedings are necessary, the +disagreements or disputes shall be referred to the Paris Courts having +jurisdiction, by the more diligent Party. + + +Version 1.0 dated 2006-09-05. diff --git a/cmake_format_conf.py b/cmake_format_conf.py new file mode 100644 index 0000000..45a1408 --- /dev/null +++ b/cmake_format_conf.py @@ -0,0 +1,240 @@ +# ---------------------------------- +# Options affecting listfile parsing +# ---------------------------------- +with section("parse"): + + # Specify structure for custom cmake functions + # additional_commands = {'foo': {'flags': ['BAR', 'BAZ'], + # 'kwargs': {'DEPENDS': '*', 'HEADERS': '*', 'SOURCES': '*'}}} + + # Override configurations per-command where available + override_spec = {} + + # Specify variable tags. + vartags = [] + + # Specify property tags. + proptags = [] + +# ----------------------------- +# Options affecting formatting. +# ----------------------------- +with section("format"): + + # Disable formatting entirely, making cmake-format a no-op + disable = False + + # How wide to allow formatted cmake files + line_width = 100 + + # How many spaces to tab for indent + tab_size = 2 + + # If true, lines are indented using tab characters (utf-8 0x09) instead of + # space characters (utf-8 0x20). In cases where the layout would + # require a fractional tab character, the behavior of the fractional + # indentation is governed by + use_tabchars = False + + # If is True, then the value of this variable indicates how + # fractional indentions are handled during whitespace replacement. If set to + # 'use-space', fractional indentation is left as spaces (utf-8 0x20). If set + # to `round-up` fractional indentation is replaced with a single tab character + # (utf-8 0x09) effectively shifting the column to the next tabstop + fractional_tab_policy = 'round-up' + + # If an argument group contains more than this many sub-groups (parg or kwarg + # groups) then force it to a vertical layout. + max_subgroups_hwrap = 2 + + # If a positional argument group contains more than this many arguments, then + # force it to a vertical layout. + max_pargs_hwrap = 3 + + # If a cmdline positional group consumes more than this many lines without + # nesting, then invalidate the layout (and nest) + max_rows_cmdline = 2 + + # If true, separate flow control names from their parentheses with a space + separate_ctrl_name_with_space = True + + # If true, separate function names from parentheses with a space + separate_fn_name_with_space = True + + # If a statement is wrapped to more than one line, than dangle the closing + # parenthesis on its own line. + dangle_parens = True + + # If the trailing parenthesis must be 'dangled' on its on line, then align it + # to this reference: `prefix`: the start of the statement, `prefix-indent`: + # the start of the statement, plus one indentation level, `child`: align to + # the column of the arguments + dangle_align = 'prefix' + + # If the statement spelling length (including space and parenthesis) is + # smaller than this amount, then force reject nested layouts. + min_prefix_chars = 4 + + # If the statement spelling length (including space and parenthesis) is larger + # than the tab width by more than this amount, then force reject un-nested + # layouts. + max_prefix_chars = 10 + + # If a candidate layout is wrapped horizontally but it exceeds this many + # lines, then reject the layout. + max_lines_hwrap = 2 + + # What style line endings to use in the output. + line_ending = 'unix' + + # Format command names consistently as 'lower' or 'upper' case + command_case = 'lower' + + # Format keywords consistently as 'lower' or 'upper' case + keyword_case = 'upper' + + # A list of command names which should always be wrapped + always_wrap = [] + + # If true, the argument lists which are known to be sortable will be sorted + # lexicographicall + enable_sort = True + + # If true, the parsers may infer whether or not an argument list is sortable + # (without annotation). + autosort = False + + # By default, if cmake-format cannot successfully fit everything into the + # desired linewidth it will apply the last, most agressive attempt that it + # made. If this flag is True, however, cmake-format will print error, exit + # with non-zero status code, and write-out nothing + require_valid_layout = False + + # A dictionary mapping layout nodes to a list of wrap decisions. See the + # documentation for more information. + layout_passes = {} + +# ------------------------------------------------ +# Options affecting comment reflow and formatting. +# ------------------------------------------------ +with section("markup"): + + # What character to use for bulleted lists + bullet_char = '*' + + # What character to use as punctuation after numerals in an enumerated list + enum_char = '.' + + # If comment markup is enabled, don't reflow the first comment block in each + # listfile. Use this to preserve formatting of your copyright/license + # statements. + first_comment_is_literal = False + + # If comment markup is enabled, don't reflow any comment block which matches + # this (regex) pattern. Default is `None` (disabled). + literal_comment_pattern = None + + # Regular expression to match preformat fences in comments default= + # ``r'^\s*([`~]{3}[`~]*)(.*)$'`` + fence_pattern = '^\\s*([`~]{3}[`~]*)(.*)$' + + # Regular expression to match rulers in comments default= + # ``r'^\s*[^\w\s]{3}.*[^\w\s]{3}$'`` + ruler_pattern = '^\\s*[^\\w\\s]{3}.*[^\\w\\s]{3}$' + + # If a comment line matches starts with this pattern then it is explicitly a + # trailing comment for the preceeding argument. Default is '#<' + explicit_trailing_pattern = '#<' + + # If a comment line starts with at least this many consecutive hash + # characters, then don't lstrip() them off. This allows for lazy hash rulers + # where the first hash int8_t is not separated by space + hashruler_min_length = 10 + + # If true, then insert a space between the first hash int8_t and remaining hash + # chars in a hash ruler, and normalize its length to fill the column + canonicalize_hashrulers = True + + # enable comment markup parsing and reflow + enable_markup = True + +# ---------------------------- +# Options affecting the linter +# ---------------------------- +with section("lint"): + + # a list of lint codes to disable + disabled_codes = [] + + # regular expression pattern describing valid function names + function_pattern = '[0-9a-z_]+' + + # regular expression pattern describing valid macro names + macro_pattern = '[0-9A-Z_]+' + + # regular expression pattern describing valid names for variables with global + # (cache) scope + global_var_pattern = '[A-Z][0-9A-Z_]+' + + # regular expression pattern describing valid names for variables with global + # scope (but internal semantic) + internal_var_pattern = '_[A-Z][0-9A-Z_]+' + + # regular expression pattern describing valid names for variables with local + # scope + local_var_pattern = '[a-z][a-z0-9_]+' + + # regular expression pattern describing valid names for privatedirectory + # variables + private_var_pattern = '_[0-9a-z_]+' + + # regular expression pattern describing valid names for public directory + # variables + public_var_pattern = '[A-Z][0-9A-Z_]+' + + # regular expression pattern describing valid names for function/macro + # arguments and loop variables. + argument_var_pattern = '[a-z][a-z0-9_]+' + + # regular expression pattern describing valid names for keywords used in + # functions or macros + keyword_pattern = '[A-Z][0-9A-Z_]+' + + # In the heuristic for C0201, how many conditionals to match within a loop in + # before considering the loop a parser. + max_conditionals_custom_parser = 2 + + # Require at least this many newlines between statements + min_statement_spacing = 1 + + # Require no more than this many newlines between statements + max_statement_spacing = 2 + max_returns = 6 + max_branches = 12 + max_arguments = 5 + max_localvars = 15 + max_statements = 50 + +# ------------------------------- +# Options affecting file encoding +# ------------------------------- +with section("encode"): + + # If true, emit the unicode byte-order mark (BOM) at the start of the file + emit_byteorder_mark = False + + # Specify the encoding of the input file. Defaults to utf-8 + input_encoding = 'utf-8' + + # Specify the encoding of the output file. Defaults to utf-8. Note that cmake + # only claims to support utf-8 so be careful when using anything else + output_encoding = 'utf-8' + +# ------------------------------------- +# Miscellaneous configurations options. +# ------------------------------------- +with section("misc"): + + # A dictionary containing any per-command configuration overrides. Currently + # only `command_case` is supported. + per_command = {} diff --git a/hls_files/generated/.empty b/hls_files/generated/.empty new file mode 100644 index 0000000..013ed0d --- /dev/null +++ b/hls_files/generated/.empty @@ -0,0 +1 @@ +Empty file \ No newline at end of file diff --git a/hls_files/templates/script_type_strmlen_endian_from_bytes.tcl.in b/hls_files/templates/script_type_strmlen_endian_from_bytes.tcl.in new file mode 100644 index 0000000..463079f --- /dev/null +++ b/hls_files/templates/script_type_strmlen_endian_from_bytes.tcl.in @@ -0,0 +1,153 @@ +# +# Copyright or © or Copr. Université de Bretagne-Sud, Lab-STICC, Bordeaux-INP, IMS +# Contributor(s) : Camille Monière (2022) +# +# camille.moniere@univ-ubs.fr, camille.moniere@ims-bordeaux.fr +# +# This software is a computer program whose purpose is to simulate and implement C-type +# to bytes FPGA IPs. +# +# This software is governed by the CeCILL-B license under French law and +# abiding by the rules of distribution of free software. You can use, +# modify and/ or redistribute the software under the terms of the CeCILL-B +# license as circulated by CEA, CNRS and INRIA at the following URL +# "http://www.cecill.info". +# +# As a counterpart to the access to the source code and rights to copy, +# modify and redistribute granted by the license, users are provided only +# with a limited warranty and the software's author, the holder of the +# economic rights, and the successive licensors have only limited +# liability. +# +# In this respect, the user's attention is drawn to the risks associated +# with loading, using, modifying and/or developing or reproducing the +# software by the user in light of its specific status of free software, +# that may mean that it is complicated to manipulate, and that also +# therefore means that it is reserved for developers and experienced +# professionals having in-depth computer knowledge. Users are therefore +# encouraged to load and test the software's suitability as regards their +# requirements in conditions enabling the security of their systems and/or +# data to be ensured and, more generally, to use and operate it in the +# same conditions as regards security. +# +# The fact that you are presently reading this means that you have had +# knowledge of the CeCILL-B license and that you accept its terms. +# + +set SCRIPT_DIR [file normalize [file dirname [info script]]] +set ROOT_DIR [file normalize "${SCRIPT_DIR}/../.."] + +set VERSION [version -short] +set XILINX_MAJOR [expr {int($VERSION)}] + +set cnt 0 +if { [expr {$argc > 0}] } { + set argp 0 + while { $argp < $argc } { + set curr [lindex $argv $argp] + if { [string index $curr 0] != "-" } { + if { $cnt == 0 } { + set NLINES $curr + set cnt [expr { $cnt + 1 }] + } elseif { $cnt == 1 } { + set EXPORT_IP $curr + set cnt [expr { $cnt + 1 }] + } elseif { $cnt == 2 } { + set RUN_IMPL $curr + set cnt [expr { $cnt + 1 }] + } + } + set argp [ expr { $argp + 1 } ] + } +} + +if { $cnt < 1 } { + set NLINES 10000 + set EXPORT_IP 0 + set RUN_IMPL 0 +} elseif { $cnt < 2 } { + set EXPORT_IP 0 + set RUN_IMPL 0 +} elseif { $cnt < 3 } { + set RUN_IMPL 0 +} + +set ENDIAN @ENDIAN@ +set TYPE @TYPE@ +set STRMLEN @STRMLEN@ +set clk "100MHz" + +if [ expr {$VERSION > 2020.0} ] { + set CFLAGS "-std=c++11 -Wno-unknown-pragmas -Wno-unused-label -Wall -DNDEBUG -DXILINX_MAJOR=${XILINX_MAJOR} -isystem ${ROOT_DIR}/hls_max_template/sources/modules -I${ROOT_DIR}/sources -I${ROOT_DIR}/CORDIC_Rotate_APFX/RomGenerators/sources" +} else { + set CFLAGS "-std=c++0x -Wno-unknown-pragmas -Wno-unused-label -Wall -DNDEBUG -DXILINX_MAJOR=${XILINX_MAJOR} -isystem ${ROOT_DIR}/hls_max_template/sources/modules -I${ROOT_DIR}/sources -I${ROOT_DIR}/CORDIC_Rotate_APFX/RomGenerators/sources" +} + + +set PROJECT_NAME "${TYPE}_${STRMLEN}_${ENDIAN}_from_bytes_ip" +open_project -reset "${PROJECT_NAME}" +set_top ${TYPE}_${STRMLEN}_${ENDIAN}_from_bytes +add_files "${ROOT_DIR}/sources/CConverter/CConverterFromBytes.cpp" -cflags "${CFLAGS}" +add_files "${ROOT_DIR}/sources/CConverter/CConverterFromBytes.hpp" -cflags "${CFLAGS}" +add_files "${ROOT_DIR}/sources/top_converters/${TYPE}_${STRMLEN}_${ENDIAN}_from_bytes.cpp" -cflags "${CFLAGS}" +add_files "${ROOT_DIR}/sources/top_converters/${TYPE}_${STRMLEN}_${ENDIAN}_from_bytes.hpp" -cflags "${CFLAGS}" +add_files -tb "${ROOT_DIR}/sources/top_converters/${TYPE}_${STRMLEN}_${ENDIAN}_from_bytes_tb.cpp" -cflags "${CFLAGS}" + +set SOLUTION_NAME "solution_auto" +if [ expr {$VERSION > 2020.0} ] { + open_solution ${SOLUTION_NAME} -flow_target vivado +} else { + open_solution ${SOLUTION_NAME} +} + +set_part {xc7k325t-ffg900-2} +create_clock -period ${clk} -name default +set_clock_uncertainty 10% + +if { [ file exists "directives.tcl" ] } { + source "directives.tcl" +} + +set_directive_interface -mode ap_ctrl_none ${TYPE}_${STRMLEN}_${ENDIAN}_from_bytes + +csim_design -clean -O -argv "${NLINES}" +csynth_design +cosim_design -O -argv "${NLINES}" + +if { $EXPORT_IP } { + config_export \ + -rtl verilog \ + -format ip_catalog \ + -description "Convert ${STRMLEN} ${TYPE} from bytes ${ENDIAN} at ${clk}" \ + -vendor "DrasLorus" \ + -display_name "${STRMLEN} ${TYPE} bus from ${ENDIAN} bytes converter ${clk}" \ + -version "0.1.00${XILINX_MAJOR}" \ + -ipname "bytes${ENDIAN}2${TYPE}_${STRMLEN}_${clk}" \ + -vivado_optimization_level 2 \ + -vivado_phys_opt route + + if [ expr {! [ file isdirectory "${ROOT_DIR}/ip" ] } ] { + if { [ file exists "${ROOT_DIR}/ip" ] } { + file remove "${ROOT_DIR}/ip" + } + file mkdir "${ROOT_DIR}/ip" + } + + if [ expr {$VERSION > 2020.0} ] { + export_design -output "${ROOT_DIR}/ip/bytes${ENDIAN}2${TYPE}_${STRMLEN}_${clk}_${XILINX_MAJOR}.zip" + } else { + export_design + set IP_FILE [glob -directory "${PROJECT_NAME}/${SOLUTION_NAME}/impl/ip" -- "*.zip"] + file copy -force -- "${IP_FILE}" "${ROOT_DIR}/ip/bytes${ENDIAN}2${TYPE}_${STRMLEN}_${clk}_${XILINX_MAJOR}.zip" + } + + if { $RUN_IMPL } { + export_design -flow impl + } +} + +close_solution + + +close_project +exit 0 diff --git a/hls_files/templates/script_type_strmlen_endian_to_bytes.tcl.in b/hls_files/templates/script_type_strmlen_endian_to_bytes.tcl.in new file mode 100644 index 0000000..c76d5db --- /dev/null +++ b/hls_files/templates/script_type_strmlen_endian_to_bytes.tcl.in @@ -0,0 +1,153 @@ +# +# Copyright or © or Copr. Université de Bretagne-Sud, Lab-STICC, Bordeaux-INP, IMS +# Contributor(s) : Camille Monière (2022) +# +# camille.moniere@univ-ubs.fr, camille.moniere@ims-bordeaux.fr +# +# This software is a computer program whose purpose is to simulate and implement C-type +# to bytes FPGA IPs. +# +# This software is governed by the CeCILL-B license under French law and +# abiding by the rules of distribution of free software. You can use, +# modify and/ or redistribute the software under the terms of the CeCILL-B +# license as circulated by CEA, CNRS and INRIA at the following URL +# "http://www.cecill.info". +# +# As a counterpart to the access to the source code and rights to copy, +# modify and redistribute granted by the license, users are provided only +# with a limited warranty and the software's author, the holder of the +# economic rights, and the successive licensors have only limited +# liability. +# +# In this respect, the user's attention is drawn to the risks associated +# with loading, using, modifying and/or developing or reproducing the +# software by the user in light of its specific status of free software, +# that may mean that it is complicated to manipulate, and that also +# therefore means that it is reserved for developers and experienced +# professionals having in-depth computer knowledge. Users are therefore +# encouraged to load and test the software's suitability as regards their +# requirements in conditions enabling the security of their systems and/or +# data to be ensured and, more generally, to use and operate it in the +# same conditions as regards security. +# +# The fact that you are presently reading this means that you have had +# knowledge of the CeCILL-B license and that you accept its terms. +# + +set SCRIPT_DIR [file normalize [file dirname [info script]]] +set ROOT_DIR [file normalize "${SCRIPT_DIR}/../.."] + +set VERSION [version -short] +set XILINX_MAJOR [expr {int($VERSION)}] + +set cnt 0 +if { [expr {$argc > 0}] } { + set argp 0 + while { $argp < $argc } { + set curr [lindex $argv $argp] + if { [string index $curr 0] != "-" } { + if { $cnt == 0 } { + set NLINES $curr + set cnt [expr { $cnt + 1 }] + } elseif { $cnt == 1 } { + set EXPORT_IP $curr + set cnt [expr { $cnt + 1 }] + } elseif { $cnt == 2 } { + set RUN_IMPL $curr + set cnt [expr { $cnt + 1 }] + } + } + set argp [ expr { $argp + 1 } ] + } +} + +if { $cnt < 1 } { + set NLINES 10000 + set EXPORT_IP 0 + set RUN_IMPL 0 +} elseif { $cnt < 2 } { + set EXPORT_IP 0 + set RUN_IMPL 0 +} elseif { $cnt < 3 } { + set RUN_IMPL 0 +} + +set ENDIAN @ENDIAN@ +set TYPE @TYPE@ +set STRMLEN @STRMLEN@ +set clk "100MHz" + +if [ expr {$VERSION > 2020.0} ] { + set CFLAGS "-std=c++11 -Wno-unknown-pragmas -Wno-unused-label -Wall -DNDEBUG -DXILINX_MAJOR=${XILINX_MAJOR} -isystem ${ROOT_DIR}/hls_max_template/sources/modules -I${ROOT_DIR}/sources -I${ROOT_DIR}/CORDIC_Rotate_APFX/RomGenerators/sources" +} else { + set CFLAGS "-std=c++0x -Wno-unknown-pragmas -Wno-unused-label -Wall -DNDEBUG -DXILINX_MAJOR=${XILINX_MAJOR} -isystem ${ROOT_DIR}/hls_max_template/sources/modules -I${ROOT_DIR}/sources -I${ROOT_DIR}/CORDIC_Rotate_APFX/RomGenerators/sources" +} + + +set PROJECT_NAME "${TYPE}_${STRMLEN}_${ENDIAN}_to_bytes_ip" +open_project -reset "${PROJECT_NAME}" +set_top ${TYPE}_${STRMLEN}_${ENDIAN}_to_bytes +add_files "${ROOT_DIR}/sources/CConverter/CConverterToBytes.cpp" -cflags "${CFLAGS}" +add_files "${ROOT_DIR}/sources/CConverter/CConverterToBytes.hpp" -cflags "${CFLAGS}" +add_files "${ROOT_DIR}/sources/top_converters/${TYPE}_${STRMLEN}_${ENDIAN}_to_bytes.cpp" -cflags "${CFLAGS}" +add_files "${ROOT_DIR}/sources/top_converters/${TYPE}_${STRMLEN}_${ENDIAN}_to_bytes.hpp" -cflags "${CFLAGS}" +add_files -tb "${ROOT_DIR}/sources/top_converters/${TYPE}_${STRMLEN}_${ENDIAN}_to_bytes_tb.cpp" -cflags "${CFLAGS}" + +set SOLUTION_NAME "solution_auto" +if [ expr {$VERSION > 2020.0} ] { + open_solution ${SOLUTION_NAME} -flow_target vivado +} else { + open_solution ${SOLUTION_NAME} +} + +set_part {xc7k325t-ffg900-2} +create_clock -period ${clk} -name default +set_clock_uncertainty 10% + +if { [ file exists "directives.tcl" ] } { + source "directives.tcl" +} + +set_directive_interface -mode ap_ctrl_none ${TYPE}_${STRMLEN}_${ENDIAN}_to_bytes + +csim_design -clean -O -argv "${NLINES}" +csynth_design +cosim_design -O -argv "${NLINES}" + +if { $EXPORT_IP } { + config_export \ + -rtl verilog \ + -format ip_catalog \ + -description "Convert ${STRMLEN} ${TYPE} to bytes ${ENDIAN} at ${clk}" \ + -vendor "DrasLorus" \ + -display_name "${STRMLEN} ${TYPE} bus to ${ENDIAN} bytes converter ${clk}" \ + -version "0.1.00${XILINX_MAJOR}" \ + -ipname "${TYPE}2bytes${ENDIAN}_${STRMLEN}_${clk}" \ + -vivado_optimization_level 2 \ + -vivado_phys_opt route + + if [ expr {! [ file isdirectory "${ROOT_DIR}/ip" ] } ] { + if { [ file exists "${ROOT_DIR}/ip" ] } { + file remove "${ROOT_DIR}/ip" + } + file mkdir "${ROOT_DIR}/ip" + } + + if [ expr {$VERSION > 2020.0} ] { + export_design -output "${ROOT_DIR}/ip/${TYPE}2bytes${ENDIAN}_${STRMLEN}_${clk}_${XILINX_MAJOR}.zip" + } else { + export_design + set IP_FILE [glob -directory "${PROJECT_NAME}/${SOLUTION_NAME}/impl/ip" -- "*.zip"] + file copy -force -- "${IP_FILE}" "${ROOT_DIR}/ip/${TYPE}2bytes${ENDIAN}_${STRMLEN}_${clk}_${XILINX_MAJOR}.zip" + } + + if { $RUN_IMPL } { + export_design -flow impl + } +} + +close_solution + + +close_project +exit 0 diff --git a/sources/CConverter/CConverterFromBytes.cpp b/sources/CConverter/CConverterFromBytes.cpp new file mode 100644 index 0000000..bd3a454 --- /dev/null +++ b/sources/CConverter/CConverterFromBytes.cpp @@ -0,0 +1,42 @@ +/* + * Copyright or © or Copr. Université de Bretagne-Sud, Lab-STICC, Bordeaux-INP, IMS + * Contributor(s) : Camille Monière (2022) + * + * camille.moniere@univ-ubs.fr, camille.moniere@ims-bordeaux.fr + * + * This software is a computer program whose purpose is to simulate and implement C-type + * to bytes FPGA IPs. + * + * This software is governed by the CeCILL-B license under French law and + * abiding by the rules of distribution of free software. You can use, + * modify and/ or redistribute the software under the terms of the CeCILL-B + * license as circulated by CEA, CNRS and INRIA at the following URL + * "http://www.cecill.info". + * + * As a counterpart to the access to the source code and rights to copy, + * modify and redistribute granted by the license, users are provided only + * with a limited warranty and the software's author, the holder of the + * economic rights, and the successive licensors have only limited + * liability. + * + * In this respect, the user's attention is drawn to the risks associated + * with loading, using, modifying and/or developing or reproducing the + * software by the user in light of its specific status of free software, + * that may mean that it is complicated to manipulate, and that also + * therefore means that it is reserved for developers and experienced + * professionals having in-depth computer knowledge. Users are therefore + * encouraged to load and test the software's suitability as regards their + * requirements in conditions enabling the security of their systems and/or + * data to be ensured and, more generally, to use and operate it in the + * same conditions as regards security. + * + * The fact that you are presently reading this means that you have had + * knowledge of the CeCILL-B license and that you accept its terms. + */ + +#ifndef _CONVERTER_FROM_BYTES_HPP_ +#define _CONVERTER_FROM_BYTES_HPP_ + + + +#endif // _CONVERTER_FROM_BYTES_HPP_ diff --git a/sources/CConverter/CConverterFromBytes.hpp b/sources/CConverter/CConverterFromBytes.hpp new file mode 100644 index 0000000..51b1aa5 --- /dev/null +++ b/sources/CConverter/CConverterFromBytes.hpp @@ -0,0 +1,95 @@ +/* + * Copyright or © or Copr. Université de Bretagne-Sud, Lab-STICC, Bordeaux-INP, IMS + * Contributor(s) : Camille Monière (2022) + * + * camille.moniere@univ-ubs.fr, camille.moniere@ims-bordeaux.fr + * + * This software is a computer program whose purpose is to simulate and implement C-type + * to bytes FPGA IPs. + * + * This software is governed by the CeCILL-B license under French law and + * abiding by the rules of distribution of free software. You can use, + * modify and/ or redistribute the software under the terms of the CeCILL-B + * license as circulated by CEA, CNRS and INRIA at the following URL + * "http://www.cecill.info". + * + * As a counterpart to the access to the source code and rights to copy, + * modify and redistribute granted by the license, users are provided only + * with a limited warranty and the software's author, the holder of the + * economic rights, and the successive licensors have only limited + * liability. + * + * In this respect, the user's attention is drawn to the risks associated + * with loading, using, modifying and/or developing or reproducing the + * software by the user in light of its specific status of free software, + * that may mean that it is complicated to manipulate, and that also + * therefore means that it is reserved for developers and experienced + * professionals having in-depth computer knowledge. Users are therefore + * encouraged to load and test the software's suitability as regards their + * requirements in conditions enabling the security of their systems and/or + * data to be ensured and, more generally, to use and operate it in the + * same conditions as regards security. + * + * The fact that you are presently reading this means that you have had + * knowledge of the CeCILL-B license and that you accept its terms. + */ + +#ifndef _CONVERTER_FROM_BYTES_HPP_ +#define _CONVERTER_FROM_BYTES_HPP_ + +#include +#include +#include + +template +class CConverterFromBytes; + +template +class CConverterFromBytes { +public: + template + static void process(hls::stream & strm_in, hls::stream & strm_out) { +#if !defined(XILINX_MAJOR) + static_assert(std::numeric_limits::is_integer, "T must be an integer C-type."); + static_assert(std::is_unsigned(), "T must be an unsigned type."); +#endif + LOOP_STR_B2T_LE: + for (uint32_t u = 0; u < stream_len; u++) { + ap_uint word_buffer = 0; + LOOP_BYTE_B2T_LE: + for (uint32_t v = 0; v < sizeofT; v++) { + const ap_uint<8> byte_buffer = strm_in.read(); + + word_buffer >>= 8; + word_buffer(sizeofT * 8 - 1, (sizeofT - 1) * 8) = byte_buffer.range(); + } + strm_out.write(word_buffer); + } + } +}; + +template +class CConverterFromBytes { +public: + template + static void process(hls::stream & strm_in, hls::stream & strm_out) { +#if !defined(XILINX_MAJOR) + static_assert(std::numeric_limits::is_integer, "T must be an integer C-type."); + static_assert(std::is_unsigned(), "T must be an unsigned type."); +#endif + LOOP_STR_B2T_BE: + for (uint32_t u = 0; u < stream_len; u++) { + ap_uint word_buffer = 0; + LOOP_BYTE_B2T_BE: + for (uint32_t v = 0; v < sizeofT; v++) { + const ap_uint<8> byte_buffer = strm_in.read(); + + word_buffer <<= 8; + word_buffer += byte_buffer; + } + strm_out.write(word_buffer); + } + } +}; + +#endif // _CONVERTER_FROM_BYTES_HPP_ diff --git a/sources/CConverter/CConverterToBytes.cpp b/sources/CConverter/CConverterToBytes.cpp new file mode 100644 index 0000000..c31faf0 --- /dev/null +++ b/sources/CConverter/CConverterToBytes.cpp @@ -0,0 +1,42 @@ +/* + * Copyright or © or Copr. Université de Bretagne-Sud, Lab-STICC, Bordeaux-INP, IMS + * Contributor(s) : Camille Monière (2022) + * + * camille.moniere@univ-ubs.fr, camille.moniere@ims-bordeaux.fr + * + * This software is a computer program whose purpose is to simulate and implement C-type + * to bytes FPGA IPs. + * + * This software is governed by the CeCILL-B license under French law and + * abiding by the rules of distribution of free software. You can use, + * modify and/ or redistribute the software under the terms of the CeCILL-B + * license as circulated by CEA, CNRS and INRIA at the following URL + * "http://www.cecill.info". + * + * As a counterpart to the access to the source code and rights to copy, + * modify and redistribute granted by the license, users are provided only + * with a limited warranty and the software's author, the holder of the + * economic rights, and the successive licensors have only limited + * liability. + * + * In this respect, the user's attention is drawn to the risks associated + * with loading, using, modifying and/or developing or reproducing the + * software by the user in light of its specific status of free software, + * that may mean that it is complicated to manipulate, and that also + * therefore means that it is reserved for developers and experienced + * professionals having in-depth computer knowledge. Users are therefore + * encouraged to load and test the software's suitability as regards their + * requirements in conditions enabling the security of their systems and/or + * data to be ensured and, more generally, to use and operate it in the + * same conditions as regards security. + * + * The fact that you are presently reading this means that you have had + * knowledge of the CeCILL-B license and that you accept its terms. + */ + +#ifndef _CONVERTER_TO_BYTES_HPP_ +#define _CONVERTER_TO_BYTES_HPP_ + + + +#endif // _CONVERTER_TO_BYTES_HPP_ diff --git a/sources/CConverter/CConverterToBytes.hpp b/sources/CConverter/CConverterToBytes.hpp new file mode 100644 index 0000000..7d8cee4 --- /dev/null +++ b/sources/CConverter/CConverterToBytes.hpp @@ -0,0 +1,93 @@ +/* + * Copyright or © or Copr. Université de Bretagne-Sud, Lab-STICC, Bordeaux-INP, IMS + * Contributor(s) : Camille Monière (2022) + * + * camille.moniere@univ-ubs.fr, camille.moniere@ims-bordeaux.fr + * + * This software is a computer program whose purpose is to simulate and implement C-type + * to bytes FPGA IPs. + * + * This software is governed by the CeCILL-B license under French law and + * abiding by the rules of distribution of free software. You can use, + * modify and/ or redistribute the software under the terms of the CeCILL-B + * license as circulated by CEA, CNRS and INRIA at the following URL + * "http://www.cecill.info". + * + * As a counterpart to the access to the source code and rights to copy, + * modify and redistribute granted by the license, users are provided only + * with a limited warranty and the software's author, the holder of the + * economic rights, and the successive licensors have only limited + * liability. + * + * In this respect, the user's attention is drawn to the risks associated + * with loading, using, modifying and/or developing or reproducing the + * software by the user in light of its specific status of free software, + * that may mean that it is complicated to manipulate, and that also + * therefore means that it is reserved for developers and experienced + * professionals having in-depth computer knowledge. Users are therefore + * encouraged to load and test the software's suitability as regards their + * requirements in conditions enabling the security of their systems and/or + * data to be ensured and, more generally, to use and operate it in the + * same conditions as regards security. + * + * The fact that you are presently reading this means that you have had + * knowledge of the CeCILL-B license and that you accept its terms. + */ + +#ifndef _CONVERTER_TO_BYTES_HPP_ +#define _CONVERTER_TO_BYTES_HPP_ + +#include +#include +#include + +template +class CConverterToBytes; + +template +class CConverterToBytes { +public: + template + static void process(hls::stream & strm_in, hls::stream & strm_out) { +#if !defined(XILINX_MAJOR) + static_assert(std::numeric_limits::is_integer, "T must be an integer C-type."); + static_assert(std::is_unsigned(), "T must be an unsigned type."); +#endif + LOOP_STR_T2B_LE: + for (uint32_t u = 0; u < stream_len; u++) { + ap_uint word_buffer = strm_in.read(); + LOOP_BYTE_T2B_LE: + for (uint32_t v = 0; v < sizeofT; v++) { + const ap_uint<8> byte_buffer = word_buffer(7, 0); + + strm_out.write(byte_buffer); + word_buffer >>= 8; + } + } + } +}; + +template +class CConverterToBytes { +public: + template + static void process(hls::stream & strm_in, hls::stream & strm_out) { +#if !defined(XILINX_MAJOR) + static_assert(std::numeric_limits::is_integer, "T must be an integer C-type."); + static_assert(std::is_unsigned(), "T must be an unsigned type."); +#endif + LOOP_STR_T2B_BE: + for (uint32_t u = 0; u < stream_len; u++) { + ap_uint word_buffer = strm_in.read(); + LOOP_BYTE_T2B_BE: + for (uint32_t v = 0; v < sizeofT; v++) { + const ap_uint<8> byte_buffer = word_buffer(sizeofT * 8 - 1, (sizeofT - 1) * 8); + + strm_out.write(byte_buffer); + word_buffer <<= 8; + } + } + } +}; + +#endif // _CONVERTER_TO_BYTES_HPP_ diff --git a/sources/top_converters/type_strmlen_endian_from_bytes.cpp.in b/sources/top_converters/type_strmlen_endian_from_bytes.cpp.in new file mode 100644 index 0000000..2d5859c --- /dev/null +++ b/sources/top_converters/type_strmlen_endian_from_bytes.cpp.in @@ -0,0 +1,41 @@ +/* + * Copyright or © or Copr. Université de Bretagne-Sud, Lab-STICC, Bordeaux-INP, IMS + * Contributor(s) : Camille Monière (2022) + * + * camille.moniere@univ-ubs.fr, camille.moniere@ims-bordeaux.fr + * + * This software is a computer program whose purpose is to simulate and implement C-type + * to bytes FPGA IPs. + * + * This software is governed by the CeCILL-B license under French law and + * abiding by the rules of distribution of free software. You can use, + * modify and/ or redistribute the software under the terms of the CeCILL-B + * license as circulated by CEA, CNRS and INRIA at the following URL + * "http://www.cecill.info". + * + * As a counterpart to the access to the source code and rights to copy, + * modify and redistribute granted by the license, users are provided only + * with a limited warranty and the software's author, the holder of the + * economic rights, and the successive licensors have only limited + * liability. + * + * In this respect, the user's attention is drawn to the risks associated + * with loading, using, modifying and/or developing or reproducing the + * software by the user in light of its specific status of free software, + * that may mean that it is complicated to manipulate, and that also + * therefore means that it is reserved for developers and experienced + * professionals having in-depth computer knowledge. Users are therefore + * encouraged to load and test the software's suitability as regards their + * requirements in conditions enabling the security of their systems and/or + * data to be ensured and, more generally, to use and operate it in the + * same conditions as regards security. + * + * The fact that you are presently reading this means that you have had + * knowledge of the CeCILL-B license and that you accept its terms. + */ + +#include "top_converters/@TYPE@_@STRMLEN@_@ENDIAN@_from_bytes.hpp" + +void @TYPE@_@STRMLEN@_@ENDIAN@_from_bytes(hls::stream & strm_in, hls::stream<@TYPE@> & strm_out) { + CConverterFromBytes<@STRMLEN@, @ENDIAN@>::process(strm_in, strm_out); +} diff --git a/sources/top_converters/type_strmlen_endian_from_bytes.hpp.in b/sources/top_converters/type_strmlen_endian_from_bytes.hpp.in new file mode 100644 index 0000000..3fa85d3 --- /dev/null +++ b/sources/top_converters/type_strmlen_endian_from_bytes.hpp.in @@ -0,0 +1,49 @@ +/* + * Copyright or © or Copr. Université de Bretagne-Sud, Lab-STICC, Bordeaux-INP, IMS + * Contributor(s) : Camille Monière (2022) + * + * camille.moniere@univ-ubs.fr, camille.moniere@ims-bordeaux.fr + * + * This software is a computer program whose purpose is to simulate and implement C-type + * to bytes FPGA IPs. + * + * This software is governed by the CeCILL-B license under French law and + * abiding by the rules of distribution of free software. You can use, + * modify and/ or redistribute the software under the terms of the CeCILL-B + * license as circulated by CEA, CNRS and INRIA at the following URL + * "http://www.cecill.info". + * + * As a counterpart to the access to the source code and rights to copy, + * modify and redistribute granted by the license, users are provided only + * with a limited warranty and the software's author, the holder of the + * economic rights, and the successive licensors have only limited + * liability. + * + * In this respect, the user's attention is drawn to the risks associated + * with loading, using, modifying and/or developing or reproducing the + * software by the user in light of its specific status of free software, + * that may mean that it is complicated to manipulate, and that also + * therefore means that it is reserved for developers and experienced + * professionals having in-depth computer knowledge. Users are therefore + * encouraged to load and test the software's suitability as regards their + * requirements in conditions enabling the security of their systems and/or + * data to be ensured and, more generally, to use and operate it in the + * same conditions as regards security. + * + * The fact that you are presently reading this means that you have had + * knowledge of the CeCILL-B license and that you accept its terms. + */ + +#ifndef _@TYPE@_@STRMLEN@_@ENDIAN@_FROM_BYTES_HPP_ +#define _@TYPE@_@STRMLEN@_@ENDIAN@_FROM_BYTES_HPP_ + +#include "CConverter/CConverterFromBytes.hpp" + +#if !defined(LE) || !defined(BE) || LE != true || BE != false +#define LE true +#define BE false +#endif + +void @TYPE@_@STRMLEN@_@ENDIAN@_from_bytes(hls::stream & strm_in, hls::stream<@TYPE@> & strm_out); + +#endif diff --git a/sources/top_converters/type_strmlen_endian_from_bytes_tb.cpp.in b/sources/top_converters/type_strmlen_endian_from_bytes_tb.cpp.in new file mode 100644 index 0000000..bba1f62 --- /dev/null +++ b/sources/top_converters/type_strmlen_endian_from_bytes_tb.cpp.in @@ -0,0 +1,142 @@ +/* + * Copyright or © or Copr. Université de Bretagne-Sud, Lab-STICC, Bordeaux-INP, IMS + * Contributor(s) : Camille Monière (2022) + * + * camille.moniere@univ-ubs.fr, camille.moniere@ims-bordeaux.fr + * + * This software is a computer program whose purpose is to simulate and implement C-type + * to bytes FPGA IPs. + * + * This software is governed by the CeCILL-B license under French law and + * abiding by the rules of distribution of free software. You can use, + * modify and/ or redistribute the software under the terms of the CeCILL-B + * license as circulated by CEA, CNRS and INRIA at the following URL + * "http://www.cecill.info". + * + * As a counterpart to the access to the source code and rights to copy, + * modify and redistribute granted by the license, users are provided only + * with a limited warranty and the software's author, the holder of the + * economic rights, and the successive licensors have only limited + * liability. + * + * In this respect, the user's attention is drawn to the risks associated + * with loading, using, modifying and/or developing or reproducing the + * software by the user in light of its specific status of free software, + * that may mean that it is complicated to manipulate, and that also + * therefore means that it is reserved for developers and experienced + * professionals having in-depth computer knowledge. Users are therefore + * encouraged to load and test the software's suitability as regards their + * requirements in conditions enabling the security of their systems and/or + * data to be ensured and, more generally, to use and operate it in the + * same conditions as regards security. + * + * The fact that you are presently reading this means that you have had + * knowledge of the CeCILL-B license and that you accept its terms. + */ + +#include "top_converters/@TYPE@_@STRMLEN@_@ENDIAN@_from_bytes.hpp" + +#include +#include +#include +#include +#include + +using namespace std; +using namespace hls; +namespace { + +#if @ENDIAN@ == BE + +void bytes2@TYPE@_cpp(const uint8_t * __restrict in, @TYPE@ & out) { + constexpr size_t sizeofT = sizeof(@TYPE@); + + @TYPE@ buffer = @TYPE@(0); + for (uint8_t byte = 0; byte < sizeofT; byte++) { + buffer |= @TYPE@(in[byte]) << ((sizeofT - byte - 1) * 8); + } + out = buffer; +} + +#elif @ENDIAN@ == LE + +void bytes2@TYPE@_cpp(const uint8_t * __restrict in, @TYPE@ & out) { + constexpr size_t sizeofT = sizeof(@TYPE@); + + @TYPE@ buffer = @TYPE@(0); + for (uint8_t byte = 0; byte < sizeofT; byte++) { + buffer |= @TYPE@(in[byte]) << (byte * 8); + } + out = buffer; +} + +#else +#error "Endianess (currently: @ENDIAN@) can be LE (true) or BE (false)" +#endif + +} // namespace + +int main(int argc, char * argv[]) { + + constexpr uint64_t rand_seed = 147689; + + mt19937_64 rng(rand_seed); + uniform_int_distribution uniform_dist(numeric_limits::min(), numeric_limits::max()); + + constexpr uint64_t n_data = uint64_t(1e6f); + constexpr size_t sizeofT = sizeof(@TYPE@); + constexpr int64_t min_runs = int64_t(1); + constexpr int64_t max_runs = int64_t(1e6f / float(@STRMLEN@)); + + int64_t n_runs = max_runs; + if (argc > 1) { + n_runs = std::max(std::min(int64_t(stoi(string(argv[1]))) / int64_t(@STRMLEN@), max_runs), min_runs); + } + + uint8_t * data_in = new uint8_t[n_data * sizeofT]; + @TYPE@ * results = new @TYPE@[n_data]; + + hls::stream strm_in; + hls::stream<@TYPE@> strm_out; + + int counted_errors = 0; + + for (int64_t u = 0; u < n_runs; u++) { + for (uint64_t v = 0; v < @STRMLEN@; v++) { + const uint64_t local_idx = u * @STRMLEN@ + v; + for (uint8_t byte = 0; byte < sizeofT; byte++) { + data_in[local_idx * sizeofT + byte] = uniform_dist(rng); + } + + bytes2@TYPE@_cpp(data_in + local_idx * sizeofT, results[local_idx]); + + for (uint8_t byte = 0; byte < sizeofT; byte++) { + strm_in.write(data_in[local_idx * sizeofT + byte]); + } + } + + @TYPE@_@STRMLEN@_@ENDIAN@_from_bytes(strm_in, strm_out); + + for (uint64_t v = 0; v < @STRMLEN@; v++) { + const uint64_t local_idx = u * @STRMLEN@ + v; + const @TYPE@ processed = strm_out.read(); + if (results[local_idx] != processed) { + counted_errors++; + if (counted_errors < 100) { + char cformat[128]; + sprintf(cformat, "0x%%0%1lullx != 0x%%0%1lullx\n", sizeofT * 2, sizeofT * 2); + fprintf(stderr, cformat, results[local_idx], processed); + } else if (counted_errors == 100) { + fprintf(stderr, "Too much errors to be reported on terminal.\n"); + } + } + } + } + + delete[] data_in; + delete[] results; + + printf("RESULTS %s, %d errors for %lu runs.\n", counted_errors == 0 ? "SUCCESS" : "FAILURE", counted_errors, n_runs); + + return counted_errors; +} diff --git a/sources/top_converters/type_strmlen_endian_to_bytes.cpp.in b/sources/top_converters/type_strmlen_endian_to_bytes.cpp.in new file mode 100644 index 0000000..7c636fe --- /dev/null +++ b/sources/top_converters/type_strmlen_endian_to_bytes.cpp.in @@ -0,0 +1,41 @@ +/* + * Copyright or © or Copr. Université de Bretagne-Sud, Lab-STICC, Bordeaux-INP, IMS + * Contributor(s) : Camille Monière (2022) + * + * camille.moniere@univ-ubs.fr, camille.moniere@ims-bordeaux.fr + * + * This software is a computer program whose purpose is to simulate and implement C-type + * to bytes FPGA IPs. + * + * This software is governed by the CeCILL-B license under French law and + * abiding by the rules of distribution of free software. You can use, + * modify and/ or redistribute the software under the terms of the CeCILL-B + * license as circulated by CEA, CNRS and INRIA at the following URL + * "http://www.cecill.info". + * + * As a counterpart to the access to the source code and rights to copy, + * modify and redistribute granted by the license, users are provided only + * with a limited warranty and the software's author, the holder of the + * economic rights, and the successive licensors have only limited + * liability. + * + * In this respect, the user's attention is drawn to the risks associated + * with loading, using, modifying and/or developing or reproducing the + * software by the user in light of its specific status of free software, + * that may mean that it is complicated to manipulate, and that also + * therefore means that it is reserved for developers and experienced + * professionals having in-depth computer knowledge. Users are therefore + * encouraged to load and test the software's suitability as regards their + * requirements in conditions enabling the security of their systems and/or + * data to be ensured and, more generally, to use and operate it in the + * same conditions as regards security. + * + * The fact that you are presently reading this means that you have had + * knowledge of the CeCILL-B license and that you accept its terms. + */ + +#include "top_converters/@TYPE@_@STRMLEN@_@ENDIAN@_to_bytes.hpp" + +void @TYPE@_@STRMLEN@_@ENDIAN@_to_bytes(hls::stream<@TYPE@> & strm_in, hls::stream & strm_out) { + CConverterToBytes<@STRMLEN@, @ENDIAN@>::process(strm_in, strm_out); +} diff --git a/sources/top_converters/type_strmlen_endian_to_bytes.hpp.in b/sources/top_converters/type_strmlen_endian_to_bytes.hpp.in new file mode 100644 index 0000000..3c96009 --- /dev/null +++ b/sources/top_converters/type_strmlen_endian_to_bytes.hpp.in @@ -0,0 +1,49 @@ +/* + * Copyright or © or Copr. Université de Bretagne-Sud, Lab-STICC, Bordeaux-INP, IMS + * Contributor(s) : Camille Monière (2022) + * + * camille.moniere@univ-ubs.fr, camille.moniere@ims-bordeaux.fr + * + * This software is a computer program whose purpose is to simulate and implement C-type + * to bytes FPGA IPs. + * + * This software is governed by the CeCILL-B license under French law and + * abiding by the rules of distribution of free software. You can use, + * modify and/ or redistribute the software under the terms of the CeCILL-B + * license as circulated by CEA, CNRS and INRIA at the following URL + * "http://www.cecill.info". + * + * As a counterpart to the access to the source code and rights to copy, + * modify and redistribute granted by the license, users are provided only + * with a limited warranty and the software's author, the holder of the + * economic rights, and the successive licensors have only limited + * liability. + * + * In this respect, the user's attention is drawn to the risks associated + * with loading, using, modifying and/or developing or reproducing the + * software by the user in light of its specific status of free software, + * that may mean that it is complicated to manipulate, and that also + * therefore means that it is reserved for developers and experienced + * professionals having in-depth computer knowledge. Users are therefore + * encouraged to load and test the software's suitability as regards their + * requirements in conditions enabling the security of their systems and/or + * data to be ensured and, more generally, to use and operate it in the + * same conditions as regards security. + * + * The fact that you are presently reading this means that you have had + * knowledge of the CeCILL-B license and that you accept its terms. + */ + +#ifndef _@TYPE@_@STRMLEN@_@ENDIAN@_TO_BYTES_HPP_ +#define _@TYPE@_@STRMLEN@_@ENDIAN@_TO_BYTES_HPP_ + +#include "CConverter/CConverterToBytes.hpp" + +#if !defined(LE) || !defined(BE) || LE != true || BE != false +#define LE true +#define BE false +#endif + +void @TYPE@_@STRMLEN@_@ENDIAN@_to_bytes(hls::stream<@TYPE@> & strm_in, hls::stream & strm_out); + +#endif diff --git a/sources/top_converters/type_strmlen_endian_to_bytes_tb.cpp.in b/sources/top_converters/type_strmlen_endian_to_bytes_tb.cpp.in new file mode 100644 index 0000000..f61039d --- /dev/null +++ b/sources/top_converters/type_strmlen_endian_to_bytes_tb.cpp.in @@ -0,0 +1,130 @@ +/* + * Copyright or © or Copr. Université de Bretagne-Sud, Lab-STICC, Bordeaux-INP, IMS + * Contributor(s) : Camille Monière (2022) + * + * camille.moniere@univ-ubs.fr, camille.moniere@ims-bordeaux.fr + * + * This software is a computer program whose purpose is to simulate and implement C-type + * to bytes FPGA IPs. + * + * This software is governed by the CeCILL-B license under French law and + * abiding by the rules of distribution of free software. You can use, + * modify and/ or redistribute the software under the terms of the CeCILL-B + * license as circulated by CEA, CNRS and INRIA at the following URL + * "http://www.cecill.info". + * + * As a counterpart to the access to the source code and rights to copy, + * modify and redistribute granted by the license, users are provided only + * with a limited warranty and the software's author, the holder of the + * economic rights, and the successive licensors have only limited + * liability. + * + * In this respect, the user's attention is drawn to the risks associated + * with loading, using, modifying and/or developing or reproducing the + * software by the user in light of its specific status of free software, + * that may mean that it is complicated to manipulate, and that also + * therefore means that it is reserved for developers and experienced + * professionals having in-depth computer knowledge. Users are therefore + * encouraged to load and test the software's suitability as regards their + * requirements in conditions enabling the security of their systems and/or + * data to be ensured and, more generally, to use and operate it in the + * same conditions as regards security. + * + * The fact that you are presently reading this means that you have had + * knowledge of the CeCILL-B license and that you accept its terms. + */ + +#include "top_converters/@TYPE@_@STRMLEN@_@ENDIAN@_to_bytes.hpp" + +#include +#include +#include +#include +#include + +using namespace std; +using namespace hls; +namespace { + +#if @ENDIAN@ == BE + +void @TYPE@2bytes_cpp(const @TYPE@ & in, uint8_t * __restrict out) { + constexpr size_t sizeofT = sizeof(@TYPE@); + for (uint8_t byte = 0; byte < sizeofT; byte++) { + out[byte] = uint8_t((in >> ((sizeofT - byte - 1) * 8)) & 0xFF); + } +} + +#elif @ENDIAN@ == LE + +void @TYPE@2bytes_cpp(const @TYPE@ & in, uint8_t * __restrict out) { + constexpr size_t sizeofT = sizeof(@TYPE@); + for (uint8_t byte = 0; byte < sizeofT; byte++) { + out[byte] = uint8_t((in >> (byte * 8)) & 0xFF); + } +} +#else +#error "Endianess (currently: @ENDIAN@) can be LE (true) or BE (false)" +#endif + +} // namespace + +int main(int argc, char * argv[]) { + + constexpr uint64_t rand_seed = 147689; + + mt19937_64 rng(rand_seed); + uniform_int_distribution<@TYPE@> uniform_dist(numeric_limits<@TYPE@>::min(), numeric_limits<@TYPE@>::max()); + + constexpr uint64_t n_data = uint64_t(1e6f); + constexpr size_t sizeofT = sizeof(@TYPE@); + constexpr int64_t min_runs = int64_t(1); + constexpr int64_t max_runs = int64_t(1e6f / float(@STRMLEN@)); + + int64_t n_runs = max_runs; + if (argc > 1) { + n_runs = std::max(std::min(int64_t(stoi(string(argv[1]))) / int64_t(@STRMLEN@), max_runs), min_runs); + } + + @TYPE@ * data_in = new @TYPE@[n_data]; + uint8_t * results = new uint8_t[n_data * sizeofT]; + + hls::stream<@TYPE@> strm_in; + hls::stream strm_out; + + int counted_errors = 0; + + for (int64_t u = 0; u < n_runs; u++) { + for (uint64_t v = 0; v < @STRMLEN@; v++) { + const uint64_t local_idx = u * @STRMLEN@ + v; + data_in[local_idx] = uniform_dist(rng); + @TYPE@2bytes_cpp(data_in[local_idx], results + local_idx * sizeofT); + + strm_in.write(data_in[local_idx]); + } + + @TYPE@_@STRMLEN@_@ENDIAN@_to_bytes(strm_in, strm_out); + + for (uint64_t v = 0; v < @STRMLEN@; v++) { + const uint64_t local_idx = u * @STRMLEN@ + v; + for (size_t byte = 0; byte < sizeofT; byte++) { + const uint8_t processed = strm_out.read(); + if (results[local_idx * (sizeofT) + byte] != processed) { + counted_errors++; + if (counted_errors < 100) { + fprintf(stderr, "0x%02x != 0x%02x\n", (uint16_t) results[local_idx * (sizeofT) + byte], (uint16_t) processed); + } else if (counted_errors == 100) { + fprintf(stderr, "Too much errors to be reported on terminal.\n"); + } + } + } + } + } + + delete[] data_in; + delete[] results; + + printf("RESULTS %s, %d errors for %lu runs.\n", counted_errors == 0 ? "SUCCESS" : "FAILURE", counted_errors, n_runs); + + return counted_errors; +}