mirror of
https://github.com/DrasLorus/HLS_Byte_Serializer.git
synced 2024-09-08 20:05:18 +02:00
154 lines
5.9 KiB
Tcl
154 lines
5.9 KiB
Tcl
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#
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# Copyright or © or Copr. Université de Bretagne-Sud, Lab-STICC, Bordeaux-INP, IMS
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# Contributor(s) : Camille Monière (2022)
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#
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# camille.moniere@univ-ubs.fr, camille.moniere@ims-bordeaux.fr
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#
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# This software is a computer program whose purpose is to simulate and implement C-type
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# to bytes FPGA IPs.
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#
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# This software is governed by the CeCILL-B license under French law and
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# abiding by the rules of distribution of free software. You can use,
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# modify and/ or redistribute the software under the terms of the CeCILL-B
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# license as circulated by CEA, CNRS and INRIA at the following URL
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# "http://www.cecill.info".
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#
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# As a counterpart to the access to the source code and rights to copy,
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# modify and redistribute granted by the license, users are provided only
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# with a limited warranty and the software's author, the holder of the
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# economic rights, and the successive licensors have only limited
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# liability.
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#
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# In this respect, the user's attention is drawn to the risks associated
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# with loading, using, modifying and/or developing or reproducing the
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# software by the user in light of its specific status of free software,
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# that may mean that it is complicated to manipulate, and that also
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# therefore means that it is reserved for developers and experienced
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# professionals having in-depth computer knowledge. Users are therefore
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# encouraged to load and test the software's suitability as regards their
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# requirements in conditions enabling the security of their systems and/or
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# data to be ensured and, more generally, to use and operate it in the
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# same conditions as regards security.
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#
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# The fact that you are presently reading this means that you have had
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# knowledge of the CeCILL-B license and that you accept its terms.
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#
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set SCRIPT_DIR [file normalize [file dirname [info script]]]
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set ROOT_DIR [file normalize "${SCRIPT_DIR}/../.."]
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set VERSION [version -short]
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set XILINX_MAJOR [expr {int($VERSION)}]
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set cnt 0
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if { [expr {$argc > 0}] } {
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set argp 0
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while { $argp < $argc } {
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set curr [lindex $argv $argp]
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if { [string index $curr 0] != "-" } {
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if { $cnt == 0 } {
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set NLINES $curr
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set cnt [expr { $cnt + 1 }]
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} elseif { $cnt == 1 } {
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set EXPORT_IP $curr
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set cnt [expr { $cnt + 1 }]
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} elseif { $cnt == 2 } {
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set RUN_IMPL $curr
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set cnt [expr { $cnt + 1 }]
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}
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}
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set argp [ expr { $argp + 1 } ]
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}
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}
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if { $cnt < 1 } {
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set NLINES 10000
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set EXPORT_IP 0
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set RUN_IMPL 0
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} elseif { $cnt < 2 } {
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set EXPORT_IP 0
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set RUN_IMPL 0
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} elseif { $cnt < 3 } {
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set RUN_IMPL 0
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}
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set ENDIAN @ENDIAN@
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set TYPE @TYPE@
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set STRMLEN @STRMLEN@
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set clk "100MHz"
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if [ expr {$VERSION > 2020.0} ] {
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set CFLAGS "-std=c++11 -Wno-unknown-pragmas -Wno-unused-label -Wall -DNDEBUG -DXILINX_MAJOR=${XILINX_MAJOR} -isystem ${ROOT_DIR}/hls_max_template/sources/modules -I${ROOT_DIR}/sources -I${ROOT_DIR}/CORDIC_Rotate_APFX/RomGenerators/sources"
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} else {
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set CFLAGS "-std=c++0x -Wno-unknown-pragmas -Wno-unused-label -Wall -DNDEBUG -DXILINX_MAJOR=${XILINX_MAJOR} -isystem ${ROOT_DIR}/hls_max_template/sources/modules -I${ROOT_DIR}/sources -I${ROOT_DIR}/CORDIC_Rotate_APFX/RomGenerators/sources"
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}
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set PROJECT_NAME "${TYPE}_${STRMLEN}_${ENDIAN}_to_bytes_ip"
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open_project -reset "${PROJECT_NAME}"
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set_top ${TYPE}_${STRMLEN}_${ENDIAN}_to_bytes
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add_files "${ROOT_DIR}/sources/CConverter/CConverterToBytes.cpp" -cflags "${CFLAGS}"
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add_files "${ROOT_DIR}/sources/CConverter/CConverterToBytes.hpp" -cflags "${CFLAGS}"
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add_files "${ROOT_DIR}/sources/top_converters/${TYPE}_${STRMLEN}_${ENDIAN}_to_bytes.cpp" -cflags "${CFLAGS}"
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add_files "${ROOT_DIR}/sources/top_converters/${TYPE}_${STRMLEN}_${ENDIAN}_to_bytes.hpp" -cflags "${CFLAGS}"
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add_files -tb "${ROOT_DIR}/sources/top_converters/${TYPE}_${STRMLEN}_${ENDIAN}_to_bytes_tb.cpp" -cflags "${CFLAGS}"
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set SOLUTION_NAME "solution_auto"
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if [ expr {$VERSION > 2020.0} ] {
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open_solution ${SOLUTION_NAME} -flow_target vivado
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} else {
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open_solution ${SOLUTION_NAME}
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}
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set_part {xc7k325t-ffg900-2}
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create_clock -period ${clk} -name default
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set_clock_uncertainty 10%
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if { [ file exists "directives.tcl" ] } {
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source "directives.tcl"
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}
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set_directive_interface -mode ap_ctrl_none ${TYPE}_${STRMLEN}_${ENDIAN}_to_bytes
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csim_design -clean -O -argv "${NLINES}"
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csynth_design
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cosim_design -O -argv "${NLINES}"
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if { $EXPORT_IP } {
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config_export \
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-rtl verilog \
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-format ip_catalog \
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-description "Convert ${STRMLEN} ${TYPE} to bytes ${ENDIAN} at ${clk}" \
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-vendor "DrasLorus" \
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-display_name "${STRMLEN} ${TYPE} bus to ${ENDIAN} bytes converter ${clk}" \
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-version "0.1.00${XILINX_MAJOR}" \
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-ipname "${TYPE}2bytes${ENDIAN}_${STRMLEN}_${clk}" \
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-vivado_optimization_level 2 \
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-vivado_phys_opt route
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if [ expr {! [ file isdirectory "${ROOT_DIR}/ip" ] } ] {
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if { [ file exists "${ROOT_DIR}/ip" ] } {
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file remove "${ROOT_DIR}/ip"
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}
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file mkdir "${ROOT_DIR}/ip"
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}
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if [ expr {$VERSION > 2020.0} ] {
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export_design -output "${ROOT_DIR}/ip/${TYPE}2bytes${ENDIAN}_${STRMLEN}_${clk}_${XILINX_MAJOR}.zip"
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} else {
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export_design
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set IP_FILE [glob -directory "${PROJECT_NAME}/${SOLUTION_NAME}/impl/ip" -- "*.zip"]
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file copy -force -- "${IP_FILE}" "${ROOT_DIR}/ip/${TYPE}2bytes${ENDIAN}_${STRMLEN}_${clk}_${XILINX_MAJOR}.zip"
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}
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if { $RUN_IMPL } {
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export_design -flow impl
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}
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}
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close_solution
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close_project
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exit 0
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